Circuit arrangement for the power supply of a two-wire sensor

• US 20030052657A1
• Filed: 08/15/2002
• Published: 03/20/2003
• Est. Priority Date: 09/19/2001
• Status: Active Grant

• Current Assignee: VEGA Grieshaber KG (Grieshaber Verwaltungsgesellschaft mbH)
• Original Assignee: VEGA Grieshaber KG (Grieshaber Verwaltungsgesellschaft mbH)
• Inventors: Koernle, Ralf, Motzer, Juergen, Woehrle, Albert
• Granted Patent: US 6,897,639 B2
• Time in Patent Office: Days
• US Class Current: 323/282
• CPC Class Codes: G05F 3/18 using Zener diodes
• CPC Class Codes: H02H 9/008 Intrinsically safe circuits
• CPC Class Codes: Y10S 323/908 Inrush current limiters

Abstract

A two-wire sensor (6) is attached to one pole of a voltage distribution source (U) by an initial connecting line (V1) in which a current-limiting resistor (R1) is positioned and is attached to the other pole by a second connecting line (V2). Parallel to the series connection consisting of the two-wire sensor (S) and the current-limiting resistor (R1) is at least one limiting diode (D1). A current regulator (SR) which is attached to the poles of the power source (U) regulates a parallel current (I) which runs parallel to the current through the two-wire sensor (D), so that there is a sum current at the poles of the power source (U) that always corresponds to the measured value delivered by the two-wire sensor (S). The regulating inputs of the current regulator (SR) are connected to the terminals of a current-sensing resistor (R2) positioned in a connecting line (V1). When a HART®-interface is used with the two-wire sensor (S) a HART®-resistor (RH) is positioned in one of the two connecting lines (V1).

Claims

1. A circuit arrangement for providing voltage to a two-wire sensor (S) which is attached to a power source (U) at one pole by an initial connecting line (V1) in which a current-limiting resistor (R1) is positioned and which is attached to the power source at the other pole by a second connecting line (V2), while at least one limiting diode (D1) is positioned parallel to the two-wire sensor (S) and the current-limiting resistor (R1),

wherein

the two poles of the power source (U) are connected by a current regulator (SR) and in one of the two connecting lines (V1) a current sensor (R1, R2) is positioned whose terminals are connected to the regulating inputs of the current regulator (SR).

2. A circuit arrangement according to claim 1,

wherein

the current-limiting resistor (R1) also serves as a current sensor.

3. A circuit arrangement according to claim 1,

wherein

a current-sensing resistor (R2) is provided as a current sensor.

4. A circuit arrangement according to claim 3,

wherein

one pole of the power source (U) is connected to one of the terminals of the two-wire sensor by a connecting line (V1) in which is positioned a series connection consisting of a current-sensing resistor (R2) and the current-limiting resistor (R1), while the other terminal of the two-wire sensor is connected by the second connecting line to the other pole of the power source (U);

one pole of the power source (U) is connected to the other pole of the power source (U) by a series connection consisting of a diode (D2) and an initial resistor (R6);

one pole of the power source (U) is connected by a second resistor (R3) to the drain electrode of a field-effect transistor (T1) whose source electrode is connected to the second connecting line (V2);

the shared node of the diode (D2) and the first resistor (R6) is connected by a third resistor (R5), and the drain electrode of the field-effect transistor (T1) is connected by a fourth resistor (R4), to the inverted input of an operational amplifier (OP) whose non-inverted input is connected to the shared node of the current-limiting resistor (R1) and the current-sensing resistor (R2) and whose outlet is attached to the gate electrode of the field-effect transistor (T1).

5. A circuit arrangement according to one of the preceding claims 1 to 4,

wherein

the two-wire sensor (S) is furnished with a HART®

-interface, and a HART®

-resistor (RH) is positioned in one of the two connecting lines (V1).

6. A circuit arrangement according to claim 1, 2, 3, 4, or 5,

wherein

a series connection consisting of a plurality of limiting diodes is positioned parallel to the series connection consisting of the current-limiting resistor (R1) and the two-wire sensor (S).

7. A circuit arrangement according to claim 6,

wherein

at least two series connections consisting of a plurality of limiting diodes are positioned in parallel fashion one relative to the other.