Integrated circuit device with bump bridges and method for making the same

• US 20030053277A1
• Filed: 08/27/2002
• Published: 03/20/2003
• Est. Priority Date: 08/29/2001
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Solo De Zaldivar, Jose, Reiner, Joachim Christian, Rzittka, Eckart
• Application Number:
  US10/228,441
• Publication Number:
  US 20030053277A1
• Time in Patent Office: Days
• US Class Current: 361/127
• CPC Class Codes: H01L 23/5221 Crossover interconnections
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Text Integrated circuit device (20) comprising a silicon substrate (21), integrated devices (22) with contacts (23.1, 23.2), an isolating layer (24) at least partially covering the integrated devices (22) and comprising conducting areas (24.1, 24.2) which establish a conductive path to the contacts (23.1, 23.2) of the integrated devices (22). A metallization level (25) with metal lines (26.1, 26.2, 26.3, 26.4) is provided which connect to one of the contacts (23.2). The metal lines (26.1, 26.2, 26.3, 26.4) are situated above the isolating layer (24). A passivation layer (27)—situated above the metallization level (25)—comprises at least two contact areas (28.1, 28.2) for partially exposing at least two of the metal lines (26.2, 26.4). A bump bridge (29) comprising a conductive, low-resistance material, is situated on the passivation layer (27). The bump bridge (29) has a high aspect ratio and provides for a conductive connection between at least two of the metal lines (26.2, 26.4). It crosses another metal line (26.3) that is situated within the metallization level (25), without making contact to this metal line (26.3), and a substantial part of the bump bridge (29) is supported by the passivation layer (27).

Claims

1. Integrated circuit device (20) comprising:

a silicon substrate (21),

integrated devices (22) with contacts (23.1, 23.2),

an isolating layer (24) at least partially covering the integrated devices (22) and comprising conducting areas (24.1, 24.2) which establish a conductive path to the contacts (23.1, 23.2) of the integrated devices (22),

a metallization level (25) with metal lines (26.1, 26.2, 26.3, 26.4) providing electrical connections to at least one of the contacts (23.2), the metal lines (26.1, 26.2, 26.3, 26.4) being situated above the isolating layer (24),

a passivation layer (27) above the metallization level (25), which comprises at least two contact areas (28.1, 28.2) for partially exposing at least two of the metal lines (26.2, 26.4),

wherein

a bump bridge (29) comprising a conductive, low-resistance material, is situated on the passivation layer (27),

the bump bridge (29) provides for a conductive connection between at least two of the metal lines (26.2, 26.4),

the bump bridge (29) crosses another metal line (26.3) that is situated within the metallization level (25), without making contact to this metal line (26.3),

the bump bridge (29) having a high aspect ratio allowing the bump bridge (29) to be connected to a substrate (1 6) after packaging, and

that a substantial part of the bump bridge (29) is supported by the passivation layer (27).

2. The integrated circuit device (20) of claim 1, wherein the low-resistance material comprises gold (Au), or titanium (Ti), or titanium-tungsten (TiW), or titanium nitride (TiN), or aluminum (Al), or copper (Cu), or Pb/Sn, or an alloy.

3. The integrated circuit device (20) of claim 1 or 2, wherein the integrated devices (22) are transistors, preferably NMOS or PMOS transistors.

4. The integrated circuit device (20) of claim 1, 2 or 3, wherein the isolating layer (24) comprises Si3N4 or SiO2.

5. The integrated circuit device (20) of claim 1, 2, 3 or 4, wherein the passivation layer (27) comprises glass, preferably PSG, or Si₃N₄, or SiO₂.

6. The integrated circuit device (20) of one of the claims 1 through 5, comprising a thin layer or a sequence of thin layers being located between an upper surface of the passivation layer (27) and the bump bridge (29).

7. The integrated circuit device (20) of one of the claims 1 through 6, comprising a thin layer, preferably a barrier layer, being located on top of the metal lines (26.2, 26.4) being exposed in the two contact areas (28.1, 28.2) and underneath the bump bridge (29).

8. The integrated circuit device (20) of one of the preceding claims, wherein the bump bridge has a thickness between 1.0 and 1000 μ

m, and preferably between 3 and 30 μ

m.

9. The integrated circuit device (20) of one of the preceding claims, wherein the bump bridge has a sheet resistance in the range of about 0.1Ω

to 0.001Ω

.

10. The integrated circuit device (20) of one of the preceding claims, wherein the bump bridge (29) interconnects two or more metal lines.

11. The integrated circuit device (20) of one of the preceding claims, comprising ESD protection means (74), wherein the bump bridge (29) provides for a low-ohmic connection between a terminal of at least one of the integrated devices (22) to the ESD protection means (74), and/or wherein the bump bridge (29) provides for a low-ohmic connection between a power supply line of the integrated circuit device (20) and the ESD protection means (74).

12. Driver circuit (61) comprising:

a plurality of integrated devices (70) each having an output contact (72) and a supply voltage contact,

a metallization level with metal lines (74, 75, 76) providing for electrical connections to the output contacts (72) and the supply voltage contacts of the integrated devices (70),

a passivation layer above the metallization level, which comprises at contact areas for partially exposing several of the metal lines,

a plurality of bump bridges comprising a conductive, low-resistance material, being situated on the passivation layer,

each of the bump bridges providing for a conductive connection between at least two of the several metal lines,

the bump bridges crossing a metal line that is situated within the metallization level, without making contact to this metal line,

the bump bridge having a high aspect ratio allowing the bump bridge to be connected to a substrate after packaging, and

that a substantial part of the bump bridge being supported by the passivation layer.

13. The driver circuit (61) of claim 12, further comprising ESD protection means (74), whereby at least some of the bump bridges (71) provide for a low-ohmic connection to or from the ESD protection means (74).

14. Display driver circuit comprising a driver circuit according to claim 12 or 13.

15. Method for making an integrated circuit device with bump bridges, comprising the steps:

providing a semiconductor substrate (21) with circuit devices (22),

providing an isolating layer (24) at least partially covering the circuit devices (22),

providing contact areas (24.1, 24.2) in the isolating layer (24),

depositing a metal layer (25),

patterning the metal layer (25) in order to define metal lines (26.1-26.4),

providing a passivation layer (27) having at least two contact areas (28.1, 28.2) for partially exposing at least two of the metal lines (26.2, 26.4),

providing a bump bridge (29), said bump bridge (29)

comprising a conductive, low-resistance material, is situated on the passivation layer (27),

providing for a conductive connection between at least two of the metal lines (26.2, 26.4),

crossing another metal line (26.3) that is situated within the metallization level (25), without making contact to this metal line (26.3),

having a high aspect ratio, and

being supported by the passivation layer (27).

16. The method of claim 15, whereby the isolating layer (24) deposited and then patterned after deposition in order to form the contact areas (24.1, 24.2) in the isolating layer (24).

17. The method of claim 15 or 16, whereby the bump bridge (29) is formed by means of electroplating or deposition.

18. The method of claim 15, 16 or 17, wherein bump bridge (29) comprises gold (Au), or titanium (Ti), or titanium-tungsten (TiW), or titanium nitride (TiN), or aluminum (Al), or copper (Cu), or Pb/Sn, or an alloy.

19. The method of one of the claims 15-18, wherein the integrated circuit device is flip-chip mounted on a substrate, whereby the bump bridges provide for a conductive connection between elements on the integrated circuit device and interconnections being part of the substrate.