2-D FIFO memory having full-width read/write capability

• US 20030053367A1
• Filed: 07/09/2001
• Published: 03/20/2003
• Est. Priority Date: 07/09/2001
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hadzic, Nihad, Condorelli, Vincenzo
• Granted Patent: US 6,556,495 B2
• Time in Patent Office: Days
• US Class Current: 365/239
• CPC Class Codes: G06F 5/065 Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence

Abstract

An apparatus and method is disclosed for selecting data in a FIFO memory array made up of a plurality of memory cells arranged in rows and columns, where each row of cells has an associated number of word lines selectively addressable by an associated row address, and each column of cells has an associated bit line that provides access to the memory cells of the associated column as enabled by the respective word lines; and the memory array includes an address decoder having an address input for receiving an input address for selecting word lines in accordance with the input address, and a programmable-width vertical pointer for providing read and write input addresses to the address input of the address decoder during associated read and write operations of the memory array, where the programmable-width vertical pointer modifies the read and write addresses during operations of the memory array and provides a FIFO memory functionality.

Claims

1. A 2-D FIFO memory comprising a plurality of memory cells arranged in rows and columns, each row of said memory cells having associated therewith an addressable word enable line, and each column of said memory cells having associated therewith a bit line, wherein each bit line provides access to memory cells of said associated column as enabled via respective addressable word enable lines, said 2-D FIFO memory further comprising:

at least one vertical pointer being disposed towards a selectable number of respective adjacent memory cells of any given row, and being operative for selectively addressing data within the given row of respective adjacent memory cells.

2. A 2-D FIFO memory as defined in claim 1 wherein each said row of memory cells further comprises a bank of memory cells selected from the memory cells comprising the row.

3. A 2-D FIFO memory as defined in claim 1, further comprising an input register.

4. A 2-D FIFO memory as defined in claim 3, further comprising an input redirection unit for redirecting the input data from the input register toward a row of memory cells.

5. A 2-D FIFO memory as defined in claim 4, wherein the input redirection unit comprises a multiplexer for receiving the input data and sending the bits of data to the memory cells.

6. A 2-D FIFO memory as defined in claim 1, further comprising an output register.

7. A 2-D FIFO memory as defined in claim 6, further comprising an output redirection unit for redirecting the output data from a row of memory cells.

8. A 2-D FIFO memory as defined in claim 7, wherein the output redirection unit comprises a multiplexer for receiving the output data and sending the bits of data to the output register.

9. A 2-D FIFO memory as defined in claim 1, wherein the at least one vertical pointer comprises a write pointer.

10. A 2-D FIFO memory as defined in claim 1, further comprising:

at least one second vertical pointer being disposed towards a selectable number of respective adjacent memory cells of any given row, and being operative for selectively addressing data within the given row of respective adjacent memory cells.

11. A 2-D FIFO memory as defined in claim 10, wherein the at least one second vertical pointer comprises a read pointer.

12. A 2-D FIFO memory as defined in claim 2, having four banks of memory cells.

13. A 2-D FIFO memory as defined in claim 12 wherein each said bank is a regular FIFO having a depth of 128 bytes and a width of 9 bits.

14. A method of processing data in a FIFO memory comprising:

determining the width corresponding to the data;

calculating the position of the data in the FIFO in accordance with the determined width; and

selecting the memory addresses corresponding to the calculated position and the determined width anywhere in the FIFO memory.

15. A method as defined in claim 14, further comprising:

receiving the data;

receiving a first number of write word enables; and

receiving a second number of read word enables.

16. A method as defined in claim 15, further comprising:

storing the data in the selected memory addresses in correspondence with the number of write word enables.

17. A method as defined in claim 16, further comprising:

retrieving the data from the selected memory addresses in correspondence with the number of read word enables.

18. A memory array comprising a plurality of memory cells arranged in rows and columns, each row of cells having associated therewith a plurality of word lines selectively addressable by an associated row address, and each column of cells having associated therewith a bit line that provides access to memory cells of said associated column as enabled via respective word lines, said memory array further comprising:

an address decoder having an address input for receiving an input address, said address decoder selecting said word lines in accordance with said input address; and

a programmable-width vertical pointer for providing read and write input addresses to the address input of said address decoder during associated read and write operations of said memory array, said programmable-width vertical pointer modifying said read and write addresses during operations of said memory array so as to provide a FIFO memory functionality.

19. A storage medium encoded with a machine readable computer program code for processing data in a FIFO memory, the storage medium including instructions for causing a computer to implement a method, the method comprising:

determining the width corresponding to the data;

calculating the position of the data in the FIFO in accordance with the determined width; and

selecting the memory addresses corresponding to the calculated position and the determined width anywhere in the FIFO memory.

20. A computer data signal for processing data in a FIFO memory, the computer data signal comprising code configured to cause a processor to implement a method, the method comprising:

determining the width corresponding to the data;

calculating the position of the data in the FIFO in accordance with the determined width; and

selecting the memory addresses corresponding to the calculated position and the determined width anywhere in the FIFO memory.