Method and apparatus for fail-safe resynchronization with minimum latency

• US 20030053489A1
• Filed: 10/28/2002
• Published: 03/20/2003
• Est. Priority Date: 10/10/1997
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Barth, Richard M., Davis, Paul G., Abhyankar, Abhijit M., Stonecypher, William F., Chan, Andy Peng-Pui, Zerbe, Jared LeVan, Ching, Michael Tak-Kei
• Granted Patent: US 6,949,958 B2
• Time in Patent Office: Days
• US Class Current: 370/503
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0045 Correction by a latch cascade
• CPC Class Codes: H04L 7/0054 Detection of the synchronisation error by features other than the received signal transition by means of signal transition H04L7/033
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Claims

1. A synchronization circuit for synchronizing data between receive and transmit mesochronous clocks, comprising:

a receive clock domain circuit for providing the data clocked by the receive clock;

a first latching circuit, coupled to an output of the receive clock domain circuit, for latching the data on a first edge of the transmit clock;

wherein the receive clock and transmit clock are mesochronous;

a second latching circuit, in parallel with the first latching circuit, for latching the data on a second edge of the transmit clock;

a multiplexing circuit, having inputs coupled to outputs of the first and second latching circuits; and

a phase measurement circuit, configured to measure a phase difference between the receive and transmit clocks and to provide a select signal to the multiplexer in accordance with the phase difference.

2. The synchronization circuit of claim 1, wherein the phase measurement circuit determines a phase difference between the receive clock and a clock in quadrature with the transmit clock;

the phase measurement circuit including a phase comparator coupled to receive the receive clock and the clock in quadrature with the transmit clock, and an integrator coupled to an output of the phase comparator; and

the synchronization circuit including a latch coupled to an output of the phase measurement circuit for latching an output signal after an initialization period.

3. The synchronization circuit of claim 1, wherein the phase measurement circuit determines a phase difference between the receive clock and a clock in quadrature with the transmit clock.

4. The synchronization circuit of claim 1 wherein the phase measurement circuit comprises:

a phase comparator coupled to receive the receive clock and the clock in quadrature with the transmit clock; and

an integrator coupled to an output of the phase comparator.

5. The synchronization circuit of claim 1 further comprising a latch coupled to an output of the phase measurement circuit for latching an output signal after an initialization period.

6. The synchronization circuit of claim 1 wherein the latching circuits are flip-flops.

7. The synchronization circuit of claim 1 further comprising a third latching circuit, connected between an output of the first latching circuit and the multiplexer, for re-timing the output of the first latching circuit to the second edge of the transmit clock signal.

8. The synchronization circuit of claim 1 further comprising a select signal latch connected to a select input of the multiplexer.

9. The synchronization circuit of claim 8, further comprising a plurality of select signal latches, for storing different select signals corresponding to different clock frequencies.

10. The synchronization circuit of claim 1 wherein the first and second latching circuits each include a precharged sense amplifier.

11. A synchronous memory bus system comprising:

a data bus having a first end and a second end;

a clock source generating a clock signal;

a clock line carrying the clock signal, the clock line having

a first clock line segment extending from the first end of the data bus to a turnaround near the second end of the data bus, and

a second clock line segment extending from the turnaround to the first end of the data bus;

a first device coupled to the data bus for transmitting data to a second device, including synchronization circuitry that receives a first transmit clock from one of the first and second clock line segments, a receive clock from the other one of the first and second clock line segments, and a second transmit clock in quadrature with the first transmit clock, wherein the receive clock and first transmit clock are mesochronous, the synchronization circuitry comprising;

a receive clock domain circuit for providing the data clocked by the receive clock;

a first latching circuit, coupled to an output of the receive clock domain circuit, for latching the data on a first edge of the second transmit clock;

a second latching circuit, in parallel with the first latching circuit, for latching the data on a second edge of the second transmit clock;

a multiplexing circuit, having inputs coupled to outputs of the first and second latching circuits; and

a phase measurement circuit, configured to measure a phase difference between the receive clock and first transmit clock and to provide a select signal to the multiplexer in accordance with the phase difference.

12. A method for synchronizing data between receive and transmit mesochronous clocks, comprising the steps of:

providing data clocked by a receive clock from a receive clock domain;

latching the data in a first latching circuit on a first edge of a transmit clock;

latching the data in a second latching circuit on a second edge of the transmit clock;

wherein the receive clock and transmit clock are mesochronous;

measuring a phase difference between the receive and transmit clocks and providing a skip signal in accordance with the phase difference; and

selecting between the first and second latching circuit based on the skip signal.

13. The method of claim 12 wherein the step of measuring a phase difference comprises determining a phase difference between the receive clock and a clock in quadrature with the transmit clock.

14. The method of claim 12 wherein the step of measuring a phase difference comprises the steps of:

comparing the receive clock and a clock in quadrature with the transmit clock; and

integrating a result of the comparing step.

15. The method of claim 12 further comprising the step of latching the skip signal after an initialization or calibration sequence.

16. The method of claim 12, further comprising latching an output of the first latching circuit with on the second edge of the transmit clock signal so as to re-time the output of the first latching circuit to the second edge of the transmit clock signal.

17. A synchronization circuit for synchronizing data between receive and transmit mesochronous clocks, comprising:

a first receive clock domain circuit for providing the data clocked by a first edge of the receive clock;

a second receive clock domain circuit for providing the data clocked by a second edge of the receive clock;

two latching circuits, coupled to an output of the received clock domain circuits, for latching the data on an edge of the transmit clock;

wherein the receive clock and transmit clock are mesochronous;

a multiplexing circuit, having inputs coupled to outputs of the two latching circuits; and

a phase measurement circuit, configured to measure a phase difference between the received and transmit clocks and to provide a selection signal to the multiplexer in accordance with the phase differences.

18. The synchronization circuit of claim 17 wherein the phase measurement circuit determines a phase difference between the receive clock and a clock in quadrature with the transmit clock.

19. The synchronization circuit of claim 17 wherein the phase measurement circuit comprises:

a phase comparator coupled to receive the receive clock and the clock in quadrature with the transmit clock; and

an integrator coupled to an output of the phase comparator.

20. The synchronization circuit of claim 17 further comprising a latch coupled to an output of the phase measurement circuit for latching an output signal after an initialization period.

21. A synchronization circuit for synchronizing data between receive and transmit mesochronous clocks, comprising:

a receive clock domain circuit for providing the data clocked by the receive clock;

an intermediate clock domain circuit latching the output of the receive clock domain circuit on an edge of an intermediate clock, wherein the intermediate clock is a phase-interpolated waveform of the receive and transmit clocks and the receive clock and transmit clock are mesochronous; and

a transmit clock domain circuit, coupled to an output of the intermediate clock domain circuit, for latching the data on an edge of the transmit clock.

22. The circuit of claim 21 further comprising:

a phase interpolator or mixer for generating the intermediate clock from the receive and transmit clocks.