Parallel interference cancellation receiver for multiuser detection of CDMA signals

• US 20030053526A1
• Filed: 04/22/2002
• Published: 03/20/2003
• Est. Priority Date: 10/19/1999
• Status: Active Grant

• Current Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Original Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Inventors: Reznik, Alexander
• Granted Patent: US 6,724,809 B2
• Time in Patent Office: Days
• US Class Current: 375/148
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 1/7103 the interference being multiple access interference
• CPC Class Codes: H04B 1/71052 using decorrelation matrix
• CPC Class Codes: H04B 1/71075 Parallel interference cancellation

Abstract

A parallel interference cancellation receiver that reduces impulse response interference using a model of the received signal similar to that used in block linear equalizers. Block linear equalizers comprise decorrelating receivers, zero-forcing receivers, minimum mean square error receivers and the like. The invention comprises an interference computation processor feedback loop for correcting the output of a direct interference canceller. The m iterative process removes interferers from the output symbols of a matched-filter. The PIC receiver uses received signal models of the various block linear equalizers that do not assume that each subchannel consists of several distinct paths. The receiver estimates the impulse response characteristic of each subchannel as a whole.

Claims

1. An interference canceller for use in a receiver that separates received communication signals (r) from a plurality of transmitters over a CDMA interface into a plurality of desired signals (d^(k)), the interference canceller comprising:

a channel estimation processor for receiving the communication signals (r) producing individual impulse response estimates (A) for the plurality of desired signals (d^(k)), said impulse response estimates coupled to a data estimation and interference canceller; and

said data estimation and interference canceller receiving the communication signals (r) and said impulse response estimates (A) and outputting the plurality of desired signals (d^(k)).

2. The interference canceller according to claim 1, wherein said channel estimation processor further comprises:

a channel estimator coupled to the communication signals (r) for outputting channel impulse response estimates (h^(k)) for the plurality of desired signals (d^(k)), said channel estimator coupled to a system response matrix assembler;

said system response matrix assembler outputting system response matrices (A_(n)^(k)) for the plurality of desired signals (d^(k)); and

said system response matrices (A_(n)^(k)) assembled into a total system response matrix (A) output.

3. The interference canceller according to claim 2, wherein said data estimation and interference canceller further comprises:

a matched-filter coupled to the communication signals (r) and said channel estimation processor output (A) for outputting estimates of the desired signals with selective signals (y) to a first input of a summer;

said summer having an output (z(m)) coupled to a direct interference canceller;

said direct interference canceller outputting scaled estimates of the desired signals with selective signals (d(m)) of the plurality of desired signals (d^(k)) to an input of an iteration counter;

said iteration counter having a first output coupled to a feedback interference processor;

said feedback interference processor outputting interference estimates (c(m)) of the selective signals to a second input of said summer; and

said interference estimates (c(m)) subtracted from said matched-filter output (y) for m iterations by said iteration counter whereby said iteration counter outputs said estimates of the desired signals (d(m)) as the plurality of desired signals (d^(k)) absent said selective signals through a second output.

4. The interference canceller according to claim 3 wherein said direct interference canceller operation defined by an S matrix and said feedback interference processor operation defined by a T matrix related by

5. The interference canceller according to claim 4 wherein said matrix S defined as

S=(diag(O))⁻

1 and

said matrix T defined as

T=O−

diag(O).

6. The interference canceller according to claim 5 wherein said objective matrix O as a zero-forcing block linear equalizer.

7. The interference canceller according to claim 5 wherein said objective matrix O as a minimum mean square error block linear equalizer.

8. The interference canceller according to claim 5 wherein said total system response matrix (A) as a decorellator and said objective matrix O as a zero-forcing block linear equalizer.

9. The interference canceller according to claim 4 wherein said matrix S defined such that said interference canceller performs cancellation of inter-symbol interference (ISI) of each selective signal and said matrix T defined such that said feedback interference processor computes multi-access interference (MAI) contributed to each selective signal by said desired signals (d^(k)).

10. The interference canceller according to claim 9 wherein said matrix S defined

11. The interference canceller according to claim 10 wherein said objective matrix O as a zero-forcing block linear equalizer.

12. The interference canceller according to claim 10 wherein said total system response matrix (A) as a decorellator and said objective matrix O as a zero-forcing block linear equalizer.

13. The interference canceller according to claim 9 wherein said matrix S defined as

14. The interference canceller according to claim 4 wherein a hard decision symbol generator coupled between said first output of said iteration counter and said feedback interference processor input producing hard decisions on said desired signal estimates (d(m)).

15. The interference canceller according to claim 14 wherein said matrix S defined as

S=(diag(O))⁻

1 and

said matrix T defined as

T=O−

diag(O).

16. The interference canceller according to claim 15 wherein said objective matrix O as a zero-forcing block linear equalizer.

17. The interference canceller according to claim 15 wherein said objective matrix O as a minimum mean square error block linear equalizer.

18. The interference canceller according to claim 15 wherein said total system response matrix (A) as a decorellator and said objective matrix O as a zero-forcing block linear equalizer.

19. The interference canceller according to claim 14 wherein said matrix S defined such that said direct interference canceller performs cancellation of inter-symbol interference (ISI) of each selective signal and said matrix T defined such that said feedback interference processor computes multi-access interference (MAI) contributed to each selective signal by said desired signals (d^(k)).

20. The interference canceller according to claim 19 wherein said matrix S defined as

21. The interference canceller according to claim 20 wherein said objective matrix O as a zero-forcing block linear equalizer.

22. The interference canceller according to claim 20 wherein said total system response matrix (A) as a decorellator and said objective matrix O as a zero-forcing block linear equalizer.

23. The interference canceller according to claim 19 further wherein said matrix S defined as

24. The interference canceller according to claim 4 wherein a non-linear soft decision symbol generator coupled between said first output of said iteration counter and said feedback interference processor input producing non-linear soft decisions on said desired signal estimates (d(m)).

25. The interference canceller according to claim 24 wherein said matrix S defined as

S=(diag(O))⁻

1 and

said matrix T defined as

T=O−

diag(O).

26. The interference canceller according to claim 25 wherein said objective matrix O as a zero-forcing block linear equalizer.

27. The interference canceller according to claim 25 wherein said objective matrix O as a minimum mean square error block linear equalizer.

28. The interference canceller according to claim 25 wherein said total system response matrix (A) as a decorellator and said objective matrix O as a zero-forcing block linear equalizer.

29. The interference canceller according to claim 24 wherein said matrix S defined such that said direct interference canceller performs cancellation of inter-symbol interference (ISI) of each selective signal and said matrix T defined such that said feedback interference processor computes multi-access interference (MAI) contributed to each selective signal by said desired signals (d^(k)).

30. The interference canceller according to claim 29 wherein said matrix S defined as

31. The interference canceller according to claim 30 wherein said objective matrix O as a zero-forcing block linear equalizer.

32. The interference canceller according to claim 30 wherein said total system response matrix (A) as a decorellator and said objective matrix O as a zero-forcing block linear equalizer.

33. The interference canceller according to claim 29 wherein said matrix S defined as

34. A method for separating received signals (r) from a plurality of transmitters over a CDMA interface into a plurality of desired signals (d^(k) ), comprising the steps of:

a) creating a total system response matrix(A) from impulse response estimates (h^(k)) from the received signals (r);

b) filtering the received signals (r) with said total system response matrix (A) producing estimates of the desired signals with selective signals (y);

c) choosing a receiver structure (O) to converge to;

d) deriving an S matrix from said receiver structure;

e) deriving a T matrix from said receiver structure;

f) scaling said filter output (y) as desired signal estimates (d(m)) by multiplying by said matrix S;

g) computing interference estimates (c(m)) by multiplying said scaled output (d(m)) by said matrix T;

h) subtracting (z(m)) said interference estimates (c(m)) from said filter output (y);

i) scaling said filter output minus said interference estimates (z(m)) as desired signal estimates (d(m)) by multiplying with said matrix S;

j) repeating steps g) through i) for m iterations; and

k) outputting said desired signal estimates (d(m)) as the plurality of desired signals (d^(k)) absent said selective signals.

35. The method according to claim 34 wherein said matrix S defined as

S=(diag(O))⁻

1 and

said matrix T defined as

T=O−

diag(O).

36. The method according to claim 35 wherein step c) comprises choosing said receiver structure (O) as a zero-forcing block linear equalizer.

37. The method according to claim 35 wherein step c) comprises choosing said receiver structure (O) as a minimum mean square error block linear equalizer.

38. The method according to claim 35 wherein step a) comprises creating said total system response matrix A as a decorellator and step c) comprises choosing said receiver structure (O) as a zero-forcing block linear equalizer.

39. The method (17) according to claim 34 wherein defining said matrix S such that said scaling performs cancellation of inter-symbol interference (ISI) of each selective signal and defining said matrix T such that said computing interference estimates computes multi-access interference (MAI) contributed to each selective signal by said desired signals (d^(k)), respectively.

40. The method according to claim 39 wherein said matrix S defined as

41. The method according to claim 40 wherein step c) comprises choosing said receiver structure (O) as a zero-forcing block linear equalizer.

42. The method according to claim 40 wherein step c) comprises creating said total system response matrix (A) as a decorellator and step c) comprises choosing said receiver structure (O) as a zero-forcing block linear equalizer.

43. The method according to claim 39 wherein said matrix S is defined as

44. The method according to claim 34 wherein step g) comprises producing hard decisions on said desired signal estimates (d(m)).

45. The method according to claim 44 wherein said matrix S defined as

S=(diag(O))⁻

1 and

said matrix T defined as

T=O−

diag(O).

46. The method according to claim 45 wherein step c) comprises choosing said receiver structure (O) as a zero-forcing block linear equalizer.

47. The method according to claim 45 wherein step c) comprises choosing said receiver structure (O) as a minimum mean square error block linear equalizer.

48. The method according to claim 45 wherein step a) comprises creating said total system response matrix A as a decorellator and step c) comprises choosing said receiver structure (O) as a zero-forcing block linear equalizer.

49. The method according to claim 44 wherein further comprises defining said matrix S such that said scaling performs cancellation of inter-symbol interference (ISI) of each selective signal and defining said matrix T such that said computing interference estimates computes multi-access interference (MAI) contributed to each selective signal by said desired signals (d^(k)), respectively.

50. The method according to claim 49 wherein said matrix S is defined by

51. The method according to claim 50 wherein step c) comprises choosing receiver structure (O) as a zero-forcing block linear equalizer.

52. The method according to claim 50 wherein step c) comprises creating said total system response matrix (A) as a decorellator and step c) comprises choosing said receiver structure (O) as a zero-forcing block linear equalizer.

53. The method (17) according to claim 49 wherein said matrix S is defined by

54. The method according to claim 34 wherein step g) is comprises producing non-linear soft decisions on said desired signal estimates (d(m)).

55. The method according to claim 54 wherein said matrix S defined as

S=(diag(O))⁻

1 and

said matrix T defined as

T=O−

diag(O).

56. The method according to claim 55 wherein step c) comprises choosing said receiver structure (O) as a zero-forcing block linear equalizer.

57. The method according to claim 55 wherein step c) comprises choosing said receiver structure (O) as a minimum mean square error block linear equalizer.

58. The method according to claim 55 wherein step a) comprises creating said total system response matrix A as a decorellator and step c) comprises choosing said receiver structure (O) as a zero-forcing block linear equalizer.

59. The method according to claim 54 further comprising defining said matrix S such that said scaling performs cancellation of inter-symbol interference (ISI) of each selective signal and defining said matrix T such that said computing interference estimates computes multi-access interference (MAI) contributed to each selective signal by said desired signals (d^(k)), respectively.

60. The method according to claim 59 wherein said matrix S is defined by

61. The method according to claim 60 wherein step c) comprises choosing said total system response matrix (A) as a zero-forcing block linear equalizer.

62. The method according to claim 60 wherein step a) comprises creating said total system response (A) as a decorellator and step c) comprises choosing said receiver structure (O) as a zero-forcing block linear equalizer.

63. The method according to claim 59 wherein said matrix S is defined by