Method for forming shallow trench isolation in semiconductor device

• US 20030054608A1
• Filed: 09/17/2001
• Published: 03/20/2003
• Est. Priority Date: 09/17/2001
• Status: Abandoned Application

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Chang, Nai-Wen, Tseng, Kuo-Shu, Chen, Yu-Tai, Hsieh, Chyei-Jer
• Application Number:
  US09/953,222
• Publication Number:
  US 20030054608A1
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The present invention discloses a method for forming shallow trench isolation in a semiconductor device, particularly a nonvolatile memory device. A dielectric layer, an amorphous silicon layer, and a mask layer are sequentially formed over a substrate. Isolation trenches are etched in the substrate through the layers. An oxide layer is thermally grown lining the sidewalls of the amorphous silicon layer and the trenches. Due to the lower oxidation rate of amorphous silicon, the liner oxide layer is thinner at the position lining the amorphous silicon layer than at the position lining the trench. The trenches are filled with an isolation layer to form shallow trench isolation (STI) structures. After removing the mask layer, the amorphous silicon layer can be converted into a polysilicon layer to serve as a floating gate for a nonvolatile memory device.

Claims

1. A method for forming a shallow trench isolation structure for a semiconductor device, comprising the steps of:

forming a dielectric layer and an amorphous silicon layer over a semiconductor substrate;

forming a mask layer over the amorphous silicon layer;

patterning the mask layer, the amorphous silicon layer, the dielectric layer, and the substrate to form a trench in the substrate;

growing a thermal oxide layer lining the sidewalls of the amorphous silicon layer and the trench, the thermal oxide layer being thinner at the position lining the amorphous silicon layer than at the position lining the trench; and

filling the trench with an isolation layer to form a shallow trench isolation (STI) structure.

2. The method as claimed in claim 1, wherein the semiconductor substrate is a silicon substrate.

3. The method as claimed in claim 1, wherein the dielectric layer comprises silicon oxide.

4. The method as claimed in claim 1, wherein the forming the amorphous silicon layer is accomplished by a low pressure chemical vapor deposition (LPCVD) process at a temperature below about 550°

C.

5. The method as claimed in claim 1, wherein the mask layer comprises silicon nitride.

6. The method as claimed in claim 1, wherein the growing of the thermal oxide layer is accomplished by thermal growth at a temperature between about 700°

C. to 1100°

C.

7. The method as claimed in claim 1, which further includes planarizing the STI structure using a chemical-mechanical polish or etch back process.

8. The method as claimed in claim 1, which further includes removing the mask layer.

9. The method as claimed in claim 8, which further includes removing the amorphous silicon layer and the dielectric layer.

10. A method for fabricating a nonvolatile memory device with shallow trench isolation, comprising the steps of:

forming a tunnel dielectric layer and an amorphous silicon layer over a substrate;

forming a mask layer over the amorphous silicon layer;

patterning the mask layer, the amorphous silicon layer, the tunnel dielectric layer, and the substrate to form a trench in the substrate;

growing a thermal oxide layer lining the sidewalls of the amorphous silicon layer and the trench, the thermal oxide layer being thinner at the position lining the amorphous silicon layer than at the position lining the trench;

filling the trench with an isolation layer to form a shallow trench isolation (STI) structure;

removing the mask layer; and

sequentially forming an inter-gate dielectric layer and a control gate layer over the substrate, and converting the amorphous silicon layer into a polysilicon layer for serving as a floating gate.

11. The method as claimed in claim 10, wherein the semiconductor substrate is a silicon substrate.

12. The method as claimed in claim 10, wherein the tunnel dielectric layer comprises silicon oxide.

13. The method as claimed in claim 10, wherein the forming the amorphous silicon layer is accomplished by a low pressure chemical vapor deposition (LPCVD) process at a temperature below about 550°

C.

14. The method as claimed in claim 10, wherein the mask layer comprises silicon nitride.

15. The method as claimed in claim 10, wherein the growing the thermal oxide layer is accomplished by thermal growth at a temperature between about 700°

C. to 1100°

C.

16. The method as claimed in claim 10, which further includes planarizing the STI structure using a chemical-mechanical polish or etch back process.

17. The method as claimed in claim 10, wherein the trench defines active regions in the substrate, and the floating gate has a larger bottom surface area relative to the active regions.