Method for manufacturing semiconductor device including two-step ashing process of N2 plasma gas and N2/H2 plasma gas

• US 20030054656A1
• Filed: 09/09/2002
• Published: 03/20/2003
• Est. Priority Date: 09/19/2001
• Status: Abandoned Application

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Soda, Eiichi
• Application Number:
  US10/237,053
• Publication Number:
  US 20030054656A1
• Time in Patent Office: Days
• US Class Current: 438/710
• CPC Class Codes: G03F 7/427 using plasma means only
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 2221/1031 Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric

Abstract

In a method for manufacturing a semiconductor device, a photoresist pattern layer is formed on an interlayer insulating layer made of inorganic material including CH₃-groups and/or H-groups. Then, the interlayer insulating layer is etched by using the photoresist pattern layer as a mask. Finally, a two-step ashing process is performed upon the photoresist pattern layer while the interlayer insulating layer is exposed. The two-step ashing process includes a first step using N₂ plasma gas and a second step using N₂/H₂ plasma gas after the first step.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a photoresist pattern layer on an interlayer insulating layer made of inorganic material including CH₃-groups and/or H-groups;

etching said interlayer insulating layer using said photoresist pattern layer as a mask; and

performing a two-step ashing process upon said photoresist pattern layer while said interlayer insulating layer is exposed,

said two-step ashing process including a first step using N₂ plasma gas and a second step using N₂/H₂ plasma gas after said first step.

2. The method as set forth in claim 1, wherein said inorganic material comprises methyl silsesquioxane.

3. The method as set forth in claim 1, wherein said inorganic material comprises hydrogen silsesquioxane.

4. The method as set forth in claim 1, wherein said inorganic material comprises methyl hydrogen silsesquioxane.

5. The method as set forth in claim 1, wherein said two-step ashing process is performed under a state where a temperature of said interlayer insulating layer is about 0°

C. to 80°

C.

6. The method as set forth in claim 1, wherein said two-step ashing process is performed under a state where said N₂ plasma gas and said N₂/H₂ plasma gas have a pressure of about 1.33 to 13.3 Pa.

7. A method for manufacturing a semiconductor device, comprising the steps of:

forming a lower wiring layer;

forming a via stopper on said lower wiring layer;

forming a first interlayer insulating layer made of inorganic material including CH₃-groups and/or H-groups on said via stopper;

forming a groove stopper on said first interlayer insulating layer;

forming a first photoresist pattern layer having a via hole on said first interlayer insulating layer;

etching said groove stopper and said first interlayer insulating layer by using said first photoresist pattern layer as a mask;

performing a first two-step ashing process upon said first photoresist pattern layer, after said groove stopper and said first interlayer insulating layer are etched;

forming a second interlayer insulating layer made of inorganic material including CH₃-groups and/or H-groups on said groove stopper after said first two-step ashing process is performed;

forming a hard mask on said second interlayer insulating layer;

forming a second photoresist pattern layer having a groove hole on said second interlayer insulating layer;

etching said hard mask, said second interlayer insulating layer and said first interlayer insulating layer by using said second photoresist pattern layer as a mask;

performing a second two-step ashing process upon said second photoresist pattern layer, after said hard mask, said second interlayer insulating layer and said first interlayer insulating layer are etched;

etching said hard mask and an exposed portion said via stopper after said second two-step ashing process is performed; and

burying an upper wiring layer in a groove within said second interlayer insulating layer and in a via hole within said first interlayer insulating layer,

each of said first and second two-step ashing processes including a first step using N₂ plasma gas and a second step using N₂/H₂ plasma gas after said first step.

8. The method as set forth in claim 7, wherein said inorganic material comprises methyl silsesquioxane.

9. The method as set forth in claim 7, wherein said inorganic material comprises hydrogen silsesquioxane.

10. The method as set forth in claim 7, wherein said inorganic material comprises methyl hydrogen silsesquioxane.

11. The method as set forth in claim 7, wherein each of said first and second two-step ashing processes is performed under a state where a temperature of said interlayer insulating layer is about 0°

C. to 80°

C.

12. The method as set forth in claim 7, wherein each of said first and second two-step ashing processes is performed under a state where said N₂ plasma gas and said N₂/H₂ plasma gas have a pressure of about 1.33 to 13.3 Pa.

13. A method for manufacturing a semiconductor device, comprising the steps of:

forming a lower wiring layer;

forming a via stopper on said lower wiring layer;

forming a first interlayer insulating layer made of inorganic material including CH₃-groups and/or H-groups on said via stopper;

forming a groove stopper on said first interlayer insulating layer;

forming a second interlayer insulating layer made of inorganic material including CH₃-groups and/or H-groups on said groove stopper;

forming a hard mask on said second interlayer insulating layer;

forming a first photoresist pattern layer having a via hole on said hard mask;

etching said hard mask, said second interlayer insulating layer, said groove stopper and said first interlayer insulating layer by using said first photoresist pattern layer as a mask;

performing a first two-step ashing process upon said first photoresist pattern layer, after said hard mask, said second interlayer insulating layer, said groove stopper and said first interlayer insulating layer are etched;

forming a second photoresist pattern layer having a groove hole on said hard mask, after said first two-step ashing process is performed;

etching said hard mask and said second interlayer insulating layer by using said second photoresist pattern layer as a mask;

performing a second two-step ashing process upon said second photoresist pattern layer, after said hard mask and said second interlayer insulating layer are etched;

etching said hard mask and an exposed portion said via stopper after said second two-step ashing process is performed; and

burying an upper wiring layer in a groove within said second interlayer insulating layer and in a via hole within said first interlayer insulating layer,

each of said first and second two-step ashing processes including a first step using N₂ plasma gas and a second step using N₂/H₂ plasma gas after said first step.

14. The method as set forth in claim 13, wherein said inorganic material comprises methyl silsesquioxane.

15. The method as set forth in claim 13, wherein said inorganic material comprises hydrogen silsesquioxane.

16. The method as set forth in claim 13, wherein said inorganic material comprises methyl hydrogen silsesquioxane.

17. The method as set forth in claim 13, wherein each of said first and second two-step ashing processes is performed under a state where a temperature of said interlayer insulating layer is about 0°

C. to 80°

C.

18. The method as set forth in claim 13, wherein each of said first and second two-step ashing processes is performed under a state where said N₂ plasma gas and said N₂/H₂ plasma gas have a pressure of about 1.33 to 13.3 Pa.

19. A method for manufacturing a semiconductor device, comprising the steps of:

forming a lower wiring layer;

forming a via stopper on said lower wiring layer;

forming a first interlayer insulating layer made of inorganic material including CH₃-groups and/or H-groups on said via stopper;

forming a groove stopper on said first interlayer insulating layer;

forming a second interlayer insulating layer made of inorganic material including CH₃-groups and/or H-groups on said groove stopper;

forming a first hard mask on said second interlayer insulating layer;

forming a second hard mask on said first hard mask;

forming a first photoresist pattern layer having a groove hole on said second hard mask;

etching said second hard mask by using said first photoresist pattern layer as a mask;

performing an ashing process upon said first photoresist pattern layer, after said second hard mask is etched;

forming a second photoresist pattern layer having a via hole on said second hard mask, after said ashing process is performed;

etching said first hard mask, said second interlayer insulating layer, said groove stopper and said first interlayer insulating layer by using said second photoresist pattern layer as a mask;

performing a two-step ashing process upon said second photoresist pattern layer, after said hard mask, said second interlayer insulating layer, said groove stopper and said first interlayer insulating layer are etched;

etching said hard mask and an exposed portion said via stopper after said two-step ashing process is performed; and

burying an upper wiring layer in a groove within said second interlayer insulating layer and in a via hole within said first interlayer insulating layer,

said two-step ashing process including a first step using N₂ plasma gas and a second step using N₂/H₂ plasma gas after said first step.

20. The method as set forth in claim 19, wherein said inorganic material comprises methyl silsesquioxane.

21. The method as set forth in claim 19, wherein said inorganic material comprises hydrogen silsesquioxane.

22. The method as set forth in claim 19, wherein said inorganic material comprises methyl hydrogen silsesquioxane.

23. The method as set forth in claim 19, wherein said two-step ashing process is performed under a state where a temperature of said interlayer insulating layer is about 0°

C. to 80°

C.

24. The method as set forth in claim 19, wherein said two-step ashing process is performed under a state where said N₂ plasma gas and said N₂/H₂ plasma gas have a pressure of about 1.33 to 13.3 Pa.