COMPOSITE MICROELECTRONIC DIELECTRIC LAYER WITH INHIBITED CRACK SUSCEPTIBILITY

• US 20030054670A1
• Filed: 09/17/2001
• Published: 03/20/2003
• Est. Priority Date: 09/17/2001
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Ming-Tsong, Chen, Shin-Kai, Wang, Shi-Wei
• Granted Patent: US 6,541,370 B1
• Time in Patent Office: Days
• US Class Current: 438/787
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Within each of a pair of methods for forming each of a pair of microelectronic fabrications with reduced cracking within each of a pair of silicon oxide dielectric layers there is employed at least one stress reducing layer. The at least one stress reducing layer is formed of a silicon and nitrogen containing dielectric material, such as a silicon nitride dielectric material or a silicon oxynitride dielectric material.

Claims

1. A method for fabricating a microelectronic fabrication comprising:

providing a substrate;

forming upon the substrate a pair of horizontally spaced topographic features;

forming upon exposed portions of the substrate and the pair of horizontally spaced topographic features a conformal silicon oxide liner layer formed employing a chemical vapor deposition method selected from the group consisting of low pressure thermal chemical vapor deposition methods and plasma enhanced chemical vapor deposition methods;

forming over the conformal silicon oxide liner layer a gap filling silicon oxide layer formed employing a method selected from the group consisting of sub-atmospheric chemical vapor deposition methods, atmospheric pressure chemical vapor deposition methods and spin-on methods;

forming over the gap filling silicon oxide layer a capping silicon oxide layer formed employing a chemical vapor deposition method selected from the group consisting of low pressure thermal chemical vapor deposition methods and plasma enhanced chemical vapor deposition methods; and

forming at least either;

(1) interposed between the conformal silicon oxide liner layer and the gap filling silicon oxide layer;

(2) interposed between the gap filling silicon oxide layer and the capping silicon oxide layer; and

(3) upon the capping silicon oxide layer, at least one stress reducing layer, wherein the at least one stress reducing layer is formed of a silicon and nitrogen containing dielectric material.

2. The method of claim 1 wherein the substrate is employed within a microelectronic fabrication selected from the group consisting of integrated circuit microelectronic fabrications, ceramic substrate microelectronic fabrications, solar cell optoelectronic microelectronic fabrications, sensor image array optoelectronic microelectronic fabrications and display image array optoelectronic microelectronic fabrications.

3. The method of claim 1 wherein the pair of horizontally spaced topographic features is selected from the group consisting of conductor structures, semiconductor structures and dielectric structures.

4. The method of claim 1 wherein the silicon and nitrogen containing dielectric material is selected from the group consisting of silicon nitride dielectric materials and silicon oxynitride dielectric materials.

5. The method of claim 1 wherein the at least one stress reducing layer is formed employing a method selected from the group consisting of low pressure thermal chemical vapor deposition (LPCVD) methods and plasma enhanced chemical vapor deposition (PECVD) methods.

6. The method of claim 1 wherein the at least one stress reducing layer is formed to a thickness of from about 200 to about 1000 angstroms.

7. A method for fabricating a microelectronic fabrication comprising:

providing a substrate;

forming upon the substrate a pair of horizontally spaced topographic features;

forming upon exposed portions of the substrate and the pair of horizontally spaced topographic features a silicon oxide passivation layer formed employing a high density plasma chemical vapor deposition method; and

forming upon the silicon oxide passivation layer a stress reducing layer formed of a silicon and nitrogen containing dielectric material.

8. The method of claim 7 wherein the substrate is employed within a microelectronic fabrication selected from the group consisting of integrated circuit microelectronic fabrications, ceramic substrate microelectronic fabrications, solar cell optoelectronic microelectronic fabrications, sensor image array optoelectronic microelectronic fabrications and display image array optoelectronic microelectronic fabrications.

9. The method of claim 7 wherein the pair of horizontally spaced topographic features is selected from the group consisting of conductor structures, semiconductor structures and dielectric structures.

10. The method of claim 7 wherein the silicon and nitrogen containing dielectric material is selected from the group consisting of silicon nitride dielectric materials and silicon oxynitride dielectric materials.

11. The method of claim 7 wherein the at least one stress reducing layer is formed employing a method selected from the group consisting of low pressure thermal chemical vapor deposition (LPCVD) methods and plasma enhanced chemical vapor deposition (PECVD) methods.

12. The method of claim 7 wherein the at least one stress reducing layer is formed to a thickness of from about 200 to about 1000 angstroms.