Method and apparatus for dynamic coalescing

• US 20030056041A1
• Filed: 09/20/2001
• Published: 03/20/2003
• Est. Priority Date: 09/20/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Feldman, David S., Connor, Patrick L.
• Granted Patent: US 6,681,275 B2
• Time in Patent Office: Days
• US Class Current: 710/58
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation

Abstract

Numerous embodiments of a method and apparatus for dynamic coalescing are disclosed.

Claims

1. An apparatus for managing electronic data comprising:

an input/output (I/O) device;

said I/O device having the capability to combine one or more fragments of electronic data, based at least in part on the data transfer rate of said I/O device and the data processing speed of an associated system bus, wherein said associated system comprises a computing platform coupled to said I/O device.

2. The apparatus of claim 1, wherein said I/O device has the capability to determine whether or not to combine data by comparing said data transfer rate with said associated system bus data processing speed.

3. The apparatus of claim 2, wherein said I/O device has the capability to combine one or more data fragments if said data transfer rate is approximately equal to said associated system bus data processing speed.

4. The apparatus of claim 2, wherein said I/O device has the capability to combine one or more data fragments if said data transfer rate exceeds said associated system bus data processing speed.

5. The apparatus of claim 1, wherein said I/O device is capable of retrieving said one or more fragments of electronic data from an associated computer platform memory.

6. The apparatus of claim 1, wherein said system bus comprises a peripheral component interconnect (PCI) protocol specification compliant or PCI-X protocol specification compliant bus.

7. The apparatus of claim 1, wherein said I/O device is configured to allow a user to determine whether to coalesce one or more data fragments.

8. A method of managing electronic data transfers comprising:

substantially determining a data transfer rate of an I/O device;

substantially determining a data processing speed of an associated computing system bus; and

combining one or more fragments of electronic data, based at least in part on said data transfer rate of said I/O device, and the data processing speed of said associated computing system bus, wherein said associated system comprises a computing platform coupled to said I/O device.

9. The method of claim 8, wherein said I/O device determines whether or not to combine data by comparing said data transfer rate with said data processing speed of an associated computing system bus.

10. The method of claim 9, wherein said determining comprises combining one or more data fragments if said data transfer rate is approximately equal to said associated system bus data processing speed.

11. The method of claim 9, wherein said determining comprises combining one or more data fragments if said data transfer rate exceeds said associated system bus data processing speed.

12. The method of claim 8, wherein said fragments of electronic data are stored on an associated computer platform memory.

13. The method of claim 8, wherein said system bus comprises a peripheral component interconnect (PCI) protocol specification compliant or PCI-X protocol specification compliant bus.

14. An article comprising:

a storage medium;

said storage medium having stored thereon instructions, that when executed, result in execution of a method of dynamic coalescing, by combining one or more fragments of electronic data, based at least in part on the data transfer rate of an I/O device and the processing speed of an associated system bus, wherein said associated system comprises a computing platform coupled to said I/O device.

15. The article of claim 14, wherein said instructions, when executed, further result in said combining of one or more fragments of electronic data by comparing said data transfer rate with said data processing speed of an associated computing system bus.

16. The article of claim 15, wherein said instructions, when executed, further result in said combining one or more data fragments if said data transfer rate is approximately equal to said associated system bus data processing speed.

17. The article of claim 15, wherein said instructions, when executed, further result in said combining one or more data fragments if said data transfer rate exceeds said associated system bus data processing speed.

18. The article of claim 14, wherein said instructions, when executed, further result in said fragments of electronic data being located on an associated computer platform memory.

19. The article of claim 14, wherein said instructions, when executed, further result in said data transfer rate comprising the connection speed to a network in bits per second, wherein said network is coupled to said I/O device.

20. The article of claim 14, wherein said instructions, when executed, further result in said associated system bus data processing speed comprising a measure in bits per second of data transfer between two locations on said system bus.

21. The article of claim 14, wherein said system bus comprises a peripheral component interconnect (PCI) protocol specification compliant or PCI-X protocol specification compliant bus.

22. The article of claim 14, wherein said instructions, when executed, further result in said I/O device being configured to allow a user to determine whether to coalesce one or more data fragments.