High-performance, superscalar-based computer system with out-of-order instruction execution
First Claim
1. A microprocessor for executing instructions obtained from an instruction store, said microprocessor comprising:
- a) means for fetching instruction sets from an instruction store, each instruction set including an instruction;
b) means, coupled to said fetching means, for buffering instruction sets, said buffering means including a first buffer and a second buffer; and
c) means, coupled to said first and second buffers, for executing instructions, said executing means including register file means for storing data in a plurality of registers, a plurality of functional unit means for processing data wherein each said functional unit means processes data in a predetermined manner, bus means for providing plural data routing paths between said register file means and said plurality of functional unit means, and means for controlling the execution of instructions.
0 Assignments
0 Petitions
Accused Products
Abstract
A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.
-
Citations
7 Claims
-
1. A microprocessor for executing instructions obtained from an instruction store, said microprocessor comprising:
-
a) means for fetching instruction sets from an instruction store, each instruction set including an instruction;
b) means, coupled to said fetching means, for buffering instruction sets, said buffering means including a first buffer and a second buffer; and
c) means, coupled to said first and second buffers, for executing instructions, said executing means including register file means for storing data in a plurality of registers, a plurality of functional unit means for processing data wherein each said functional unit means processes data in a predetermined manner, bus means for providing plural data routing paths between said register file means and said plurality of functional unit means, and means for controlling the execution of instructions. - View Dependent Claims (2, 3, 4)
-
-
5. A microprocessor comprising:
-
a) means for obtaining a predetermined sequence of instructions to be executed, wherein an instruction of said predetermined sequence of instructions includes a register reference;
b) means for storing respective data in a plurality of registers including a predetermined register and a temporary register; and
c) means, coupled to said obtaining means, for sequentially executing said predetermined sequence of instructions, said executing means including means for directing the storage of data by an a-sequentially executed instruction to said temporary register where the register referenced by said a-sequentially executed instruction is said predetermined register.
-
-
6. A microprocessor comprising:
-
a) means for storing data in a plurality of registers identifiable by register references, said plurality of registers including a predetermined register and a temporary register;
b) means for obtaining a predetermined sequence of instructions to be executed, wherein an instruction of said predetermined sequence of instructions includes a register reference;
c) executing means, coupled to said obtaining means, for a-sequentially executing said predetermined sequence of instructions, said executing means including means, coupled to said storing means, for selecting saied temporary register where the sequential execution of said instruction provides said register reference to select said predetermined register for the storage of data. - View Dependent Claims (7)
-
Specification