THREE-DIMENSIONAL DEVICE

• US 20030057423A1
• Filed: 10/25/1999
• Published: 03/27/2003
• Est. Priority Date: 03/02/1998
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: INOUE, SATOSHI, SHIMODA, TATSUYA
• Granted Patent: US 6,846,703 B2
• Time in Patent Office: Days
• US Class Current: 257/80
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0694 comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 31/101 : Devices sensitive to infrared, visible or ultraviolet radiation
• CPC Class Codes: H10B 10/125 : the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: Y10S 438/977 : Thinning or removal of substrate

Abstract

A memory IC 10a includes a substrate (substrate on the transfer destination side) 21, and a memory cell array 71, a memory cell array 72, and a memory cell array 73 deposited on the substrate 21. The memory cell arrays 71, 72, and 73 are deposited, in that order, from the lower side in FIG. 21 by a method for transferring a thin film configuration. The method for the transfer includes the steps of forming a thin film device layer (memory cell array) on a support substrate with a separable layer therebetween, and irradiating the separable layer with light to cause a separation in the separable layer and/or at an interface so that the thin film device layer on the support substrate is transferred to the substrate 21.

Claims

1. A three-dimensional device comprising a plurality of thin film device layers deposited in a thickness direction, each thin film device layer being disposed in a predetermined region in a planar direction, wherein at least one of the thin film device layers is deposited by a transfer method.

3. The three-dimensional device according to one of claims 1 and 2, wherein the transfer method comprises the steps of forming a thin film device layer on a support substrate with a separable layer therebetween, and irradiating the separable layer with light to cause a separation in the separable layer and/or at an interface so that the thin film device layer on the support substrate is transferred to a substrate of the three-dimensional device.

4. The three-dimensional device according to claim 3, wherein the separation of the separable layer is caused by breakage or weakening of interatomic or intermolecular bonds in a material constituting the separable layer.

5. The three-dimensional device according to claim 3, wherein the separation of the separable layer is caused by evolution of gas from a material constituting the separable layer.

6. The three-dimensional device according to claim 3, wherein the light is a laser beam.

7. The three-dimensional device according to claim 3, wherein the separable layer comprises any one of amorphous silicon, ceramic, metal, and organic polymeric material.

8. The three-dimensional device according to one of claims 1 and 2, wherein the thin film device layer comprises connecting electrodes, the connecting electrodes electrically connecting two adjacent thin film device layers to each other.

9. The three-dimensional device according to claim 8, wherein the connecting electrodes are provided on both surfaces of the thin film device layer.

10. The three-dimensional device according to claim 8, wherein two adjacent thin film device layers are joined to each other with an anisotropic conductive film therebetween.

11. The three-dimensional device according to one of claims 1 and 2, wherein in two selected layers of the thin film device layers, one layer has a light-emitting section and the other layer has a light-receiving section, the light-emitting section and the light-receiving section enabling optical communication between the two layers.

12. The three-dimensional device according to one of claims 1 and 2, wherein the thin film device layer deposited by transferring is formed simultaneously with at least one of the other thin film device layers.

13. The three-dimensional device according to one of claims 1 and 2, wherein at least one of the thin film device layers comprises a plurality of thin film transistors.

14. The three-dimensional device according to one of claims 1 and 2, wherein at least one of the thin film device layers comprises a memory cell array.

15. The three-dimensional device according to one of claims 1 and 2, wherein a plurality of layers among the thin film device layers comprise one memory.

16. The three-dimensional device according to one of claims 1 and 2, wherein at least one of the thin film device layers comprises a memory cell array, and at least one of the other thin film device layers comprises a logic circuit.

17. The three-dimensional device according to claim 16, wherein the logic circuit drives the memory cell array.

18. The three-dimensional device according to claim 16, wherein the logic circuit and the memory cell array are formed in accordance with different design rules.

19. The three-dimensional device according to claim 16, wherein the logic circuit and the memory cell array are formed in accordance with different design parameters.

20. The three-dimensional device according to claim 16, wherein the logic circuit and the memory cell array are formed by different fabricating processes.

2. A three-dimensional device comprising a plurality of thin film device layers deposited on a base in a thickness direction for constituting a three-dimensional circuit, each thin film device layer constituting a circuit disposed in a predetermined region extending in a planar direction, wherein at least one of the thin film device layers is deposited by a transfer method.