Production of single-pole components

• US 20030057442A1
• Filed: 09/16/2002
• Published: 03/27/2003
• Est. Priority Date: 12/22/1999
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Lanois, Frederic
• Granted Patent: US 6,903,413 B2
• Time in Patent Office: Days
• US Class Current: 257/200
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

The invention relates to a vertical-type single-pole component, comprising regions (34) with a first type of conductivity (P) which are embedded in a thick layer (32) with a second type of conductivity (N). Said regions are distributed over at least one same horizontal level and are independent of each other. The regions also underlie an insulating material.

Claims

1. A single-pole component of vertical type, including regions (641, 642) of a first conductivity type (P) buried in a thick layer (62) of a second conductivity type (N), said regions being distributed over at least one same horizontal level and being independent from one another, characterized in that said independent regions are buried under, at side or around columns filled with an insulating material (70).

2. The component of claim 1, characterized in that it includes at least two levels, the independent regions (641,642) of successive levels being substantially vertically aligned.

3. The component of claim 2, characterized in that the independent regions (641) are rings.

4. The component of claim 3, characterized in that the deepest level includes non ring-shaped regions (642).

5. A method of manufacturing a single-pole component of vertical type in a silicon substrate (61) of a determined conductivity type (N), characterized in that it includes the steps of:

a) forming openings (66) in a thick silicon layer (62) covering the substrate, doped of the same conductivity type as said substrate, but more lightly;

b) coating the walls and bottoms of the openings with a silicon oxide layer (67);

c) forming, by implantation/diffusion through the opening bottoms, regions (641) of the conductivity type opposite (P) to that of the substrate; and

d) filling the openings with an insulating material (70).

6. The method of claim 5, characterized in that, before step d) of filling the openings (66, 68), steps a) to c) are repeated at least once, the initial openings being continued into the thick silicon layer (62).

7. The method of claim 5 or 6, characterized in that the silicon layer (62) of the same given type of conductivity (N) as the substrate (61) is intended for forming the cathode of a Schottky diode.

8. The method of claim 5 or 6, characterized in that the silicon layer of same conductivity type (N) as the substrate is intended for forming the drain of a MOS transistor.