Semiconductor device and method of manufacturing the same

• US 20030057505A1
• Filed: 09/17/2002
• Published: 03/27/2003
• Est. Priority Date: 09/25/2001
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Inoue, Susumu, Ebina, Akihiko
• Granted Patent: US 6,891,271 B2
• Time in Patent Office: Days
• US Class Current: 257/411
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A semiconductor device having memory cells. Each of the memory cells has a word gate formed over a semiconductor substrate with a first gate insulating layer interposed, an impurity layer, and first and second control gates in the shape of sidewalls. The first and second control gates adjacent to each other with the impurity layer interposed are connected to a common contact section. The common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer. The third contact conductive layer is formed over the first and second contact conductive layers.

Claims

1. A semiconductor device comprising a memory region in which non-volatile memory devices are arranged in a matrix of rows and columns to form a memory cell array, wherein:

each of the non-volatile memory devices has a word gate formed over a semiconductor layer with a first gate insulating layer interposed, an impurity layer formed in the semiconductor layer to form a source region or a drain region, and sidewall-shaped first and second control gates formed on the opposite sides of the word gate;

each of the first and second control gate faces the semiconductor layer with a second gate insulating layer interposed, and also faces the word gate with a side insulating layer interposed;

the first and second control gates extend in a first direction;

the first and second control gates adjacent to each other in a second direction intersecting the first direction with the impurity layer interposed are connected to a common contact section;

the common contact section includes a first contact conductive layer, a second contact conductive layer, and a pad-shaped third contact conductive layer;

the second contact conductive layer is continuous with the first and second control gates and disposed inside the first contact conductive layer; and

the third contact conductive layer is disposed over the first and second contact conductive layers.

2. The semiconductor device as defined in claim 1, wherein:

the first contact conductive layer is formed of the same material as the word gate;

the second contact conductive layer is formed of the same material as the first and second control gates; and

the third contact conductive layer is formed of the same material as a word line connected to the word gate.

3. The semiconductor device as defined in claim 1, wherein:

the first contact conductive layer is disposed over the semiconductor layer with a first contact insulating layer interposed;

the second contact conductive layer is disposed over the semiconductor layer with a second contact insulating layer interposed;

the first contact insulating layer is formed of the same material as the first gate insulating layer; and

the second contact insulating layer is formed of the same material as the second gate insulating layer.

4. The semiconductor device as defined in claim 3,

wherein the second contact conductive layer is disposed inside the first contact conductive layer with the second contact insulating layer interposed.

5. The semiconductor device as defined in claim 3,

wherein the second contact insulating layer is formed of the same material as the side insulating layer.

6. The semiconductor device as defined in claim 1,

wherein the second contact conductive layer has a depression in which a third contact insulating layer is buried.

7. The semiconductor device as defined in claim 1,

wherein a top surface of the side insulating layer is located at a position higher than the first and second control gates.

8. The semiconductor device as defined in claim 1,

wherein the first and second control gates adjacent to each other are covered by an insulating layer.

9. The semiconductor device as defined in claim 1,

wherein the common contact section is adjacent to an end portion of the impurity layer.

10. The semiconductor device as defined in claim 9, wherein:

a plurality of the impurity layers are provided;

a plurality of the common contact sections are provided; and

the common contact sections are respectively provided alternately on one or the other end portions of the impurity layers.

11. The semiconductor device as defined in claim 1,

wherein the second gate insulating layer and the side insulating layer are a multi-layer stack of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.

12. A method of manufacturing a semiconductor device having a memory region in which non-volatile memory devices are arranged in a matrix of rows and columns to form a memory cell array, the method comprising the steps of:

forming a first insulating layer to be formed into a first gate insulating layer over a semiconductor layer;

forming a first conductive layer over the first insulating layer;

forming a stopper layer over the first conductive layer;

patterning the first conductive layer and the stopper layer to form a gate layer;

forming a second gate insulating layer at least over the semiconductor layer;

forming a side insulating layer on the opposite sides of the gate layer;

forming a second conductive layer in the memory region;

forming a mask on the second conductive layer over a region in which a common contact section is formed;

forming first and second control gates in the shape of sidewalls and a second contact conductive layer by anisotropically etching the second conductive layer;

forming a second insulating layer in the memory region;

polishing the second insulating layer and the second conductive layer by a chemical mechanical polishing method so that the stopper layer is exposed;

removing the stopper layer;

forming an impurity layer which forms a source region or a drain region in the semiconductor layer; and

forming a third conductive layer in the memory region and then patterning the gate layer and the third conductive layer to form first and third contact conductive layers in the region in which the common contact section is formed and to form a word gate and a word line connected to the word gate.

13. The method of manufacturing a semiconductor device as defined in claim 12,

wherein the second gate insulating layer and the side insulating layer are a multi-layer stack of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, and are formed in the same step.

14. The method of manufacturing a semiconductor device as defined in claim 12, wherein:

the first contact conductive layer is formed in the same step as the word gate, the second contact conductive layer is formed in the same step as the first and second control gates, and the third contact conductive layer is formed in the same step as the word line.

15. The method of manufacturing a semiconductor device as defined in claim 12, further comprising the step of:

forming a first contact insulating layer over the semiconductor layer, and forming a second contact insulating layer over the semiconductor layer and on the opposite sides of the first contact conductive layer, both in the region in which the common contact section is formed,

wherein the first contact insulating layer is formed in the same step as the first gate insulating layer; and

wherein the second contact insulating layer is formed in the same step as the second gate insulating layer and the side insulating layer.

16. The method of manufacturing a semiconductor device as defined in claim 12,

wherein a top surface of the side insulating layer is located at a position higher than the first and second control gates.

17. The method of manufacturing a semiconductor device as defined in claim 12,

wherein the first and second control gates adjacent to each other with the impurity layer interposed, are covered by a buried insulating layer, in the step of polishing the second insulating layer by the chemical mechanical polishing method.

18. The method of manufacturing a semiconductor device as defined in claim 12,

wherein the common contact section is adjacent to an end portion of the impurity layer.

19. The method of manufacturing a semiconductor device as defined in claim 12, wherein:

a plurality of the impurity layers are provided;

a plurality of the common contact sections are provided; and

the common contact sections are respectively provided alternately on one or the other end portions of the impurity layers.