Circuit for measuring changes in capacitor gap using a switched capacitor technique

• US 20030057967A1
• Filed: 12/19/2001
• Published: 03/27/2003
• Est. Priority Date: 09/24/2001
• Status: Active Grant

• Current Assignee: Institute of Microelectronics
• Original Assignee: Institute of Microelectronics
• Inventors: Lien, Wee Liang
• Granted Patent: US 6,639,414 B2
• Time in Patent Office: Days
• US Class Current: 324/683
• CPC Class Codes: G01R 31/64 Testing of capacitors

Abstract

Disclosed is a single-stage, switched capacitor circuit for measuring changes in a variable by measuring changes in a capacitor gap. The change in the capacitor gap corresponds directly to a change in a measurable variable, such as pressure and acceleration, and thus a change in voltage. The circuit includes at least one reference capacitor, a sensor capacitor, a plurality of switches responsive to a timing device, and a device for generating substantially constant reference voltages. The sensor circuit does not result in a DC offset value, but results in the AC component of the voltage being directly proportional to the change in the variable through a substantially constant voltage is supplied to a node near the sensor capacitance. The circuit may be trimmed using a digital to analog converter and/or capacitors coupled in parallel.

Claims

1. A capacitive sensor circuit for measuring changes in a variable that can be measured according to changes in capacitor gap, the circuit comprising:

an operational amplifier including an inverting input terminal, a noninverting input terminal, and an output terminal, wherein said noninverting input terminal is operatively coupled to ground;

a first capacitor coupled to said inverting input of said operational amplifier, wherein the first capacitor is a reference capacitor;

a second capacitor coupled between the inverting input terminal and the output terminal of said operational amplifier, wherein said second capacitor is a sensor capacitor and wherein a reference node is connected to said second capacitor;

a timing device, said timing device having two phases, said two phases including a first phase and a second phase, wherein the two phases are nonoverlapping phases;

a plurality of switching devices, wherein said switching devices include a first group of switches and a second group of switches, wherein each group of said switches are responsive to a phase of said timing device, wherein said first group of switches closes during a first phase of said timing device and said second group of switches closes during a second phase of said timing device;

a plurality of voltage generating devices, wherein each of said voltage generating devices is operatively coupled to the circuit via a switch thereby generating a substantially constant voltage to the circuit;

wherein during the first phase of the clock, a first substantially constant reference voltage is supplied to the first capacitor via a first switch, and a second substantially constant reference voltage is supplied via a second switch to the reference node operatively connected to said second capacitor, thereby canceling DC offset voltage;

wherein during the second phase of the clock, a third substantially constant reference voltage is supplied via a third switch to the first capacitor; and

wherein the first operational amplifier includes one amplifier stage;

such that the electrical signal output from the output terminal of the operational amplifier is correlated to a change in a variable measurable by change in a capacitor gap.

2. The circuit of claim 1 wherein the variable measurable by a change in a capacitor gap is pressure.

3. The circuit of claim 1 wherein the variable measurable by a change in a capacitor gap is acceleration.

4. The circuit of claim 1 wherein a voltage generating device is a bias circuit for generating bias voltages.

5. The circuit of claim 4 wherein the bias circuit includes four resistors being a first resistor, a second resistor, a third resistor and a fourth resistor, and three operational amplifiers being a second operational amplifier, a third operational amplifier, and a fourth operational amplifier and wherein the second operational amplifier is coupled to a junction between the first and second resistors, wherein the third operational amplifier is coupled to a junction between the second and third resistors, wherein the fourth operational amplifier is coupled to a junction between the third and fourth resistors, wherein the resistors are coupled in series to each other in order of the first resistor, the second resistor, the third resistor and the fourth resistor.

6. The circuit of claim 4 wherein the voltage generating devices include at least one voltage divider and a unity gain buffer.

7. The circuit of claim 1 wherein the timing device is a two-phase nonoverlapping clock.

8. The circuit of claim 1 wherein voltage is the electrical signal output from the output terminal of the operational amplifier that is correlated to a change in a variable measurable by change in a capacitor gap.

9. The circuit of claim 1 wherein the substantially constant supply voltages generated by the voltage generating devices are trimmed to account for variations in capacitance for said second capacitor.

10. The circuit of claim 9 wherein the circuit further includes a digital to analog converter that generates a digital to analog converter voltage for trimming substantially constant supply voltages.

11. The circuit of claim 1 wherein a ratio of the sensor capacitance prior to a change in capacitor gap and the capacitance of the reference capacitor is trimmed to account for variations in capacitance for said second capacitor.

12. The circuit of claim 1, further comprising:

a third capacitor coupled, in said first phase, in a feedback loop from the inverting input of said first operational amplifier and the output of said first operational amplifier.

13. A fully differential capacitive sensor circuit for measuring changes in a variable measurable by changes in capacitor gap, the circuit comprising:

an operational amplifier including an inverting input terminal, a noninverting input terminal, an inverting output terminal, a noninverting output terminal, and a third output terminal, wherein said third output terminal is operatively coupled to ground;

a first capacitor coupled to said inverting input of said operational amplifier, wherein the first capacitor is a reference capacitor;

a second capacitor coupled in series to the inverting input terminal and the noninverting output terminal of said operational amplifier, wherein said second capacitor is a sensor capacitor wherein a reference node is connected to said second capacitor, wherein said first capacitor is a reference for said second capacitor;

a third capacitor coupled to said noninverting input of said first operational amplifier, wherein said third capacitor is a reference capacitor;

a fourth capacitor coupled in series to the noninverting input of said first operational amplifier and the inverting output terminal of said operational amplifier, wherein said fourth capacitor is a sensor capacitor and wherein said third capacitor is a reference capacitor for said fourth capacitor, and wherein a second reference node is connected to said fourth capacitor;

a timing device, said timing device having two phases, said two phases including a first phase and a second phase;

a plurality of switching devices, wherein said switching devices include a first group of switches and a second group of switches, wherein each group of said switches are responsive to a phase of said timing device, wherein said first group of switches closes during a first phase of said timing device and said second group of switches closes during a second phase of said timing device;

a plurality of voltage generating devices, wherein each of said voltage generating devices is operatively coupled to the circuit via a switch thereby generating a substantially constant voltage to the circuit;

insulating device for insulating the second capacitor from the fourth capacitor;

wherein during the first phase of the clock, a first substantially constant reference voltage is supplied via a first switch to the first capacitor, a second substantially constant reference voltage is supplied via a second switch to the second capacitor, and a third substantially constant reference voltage is supplied via a third switch to the third capacitor and a fourth substantially constant voltage is supplied via a fourth switch to the fourth capacitor, wherein the first and third substantially constant reference voltages are positive and said second and fourth substantially constant reference voltages are negative, and said second substantially constant voltage is supplied via said second switch to the reference node operatively connected to said second capacitor, thereby canceling DC offset voltage, and wherein said fourth substantially constant voltage is supplied via said fourth switch to said second reference node operatively connected to said fourth capacitor, thereby canceling DC offset voltage and wherein the second and fourth substantially constant voltages are negative;

wherein during a second phase of the clock, a fifth substantially constant reference voltage is supplied via a fifth switch to the first capacitor, and a sixth substantially constant reference voltage is supplied via a third switch to the third capacitor, wherein the fifth and sixth substantially constant reference voltages are negative; and

wherein the first operational amplifier includes one amplifier stage;

such that the electrical signal output from the inverting output terminal of the operational amplifier and the electrical signal output from the noninverting output terminal of the operational amplifier are correlated to a change in a variable measurable by change in a capacitor gap.

14. The circuit of claim 13 wherein the variable measurable by a change in a capacitor gap is pressure.

15. The circuit of claim 13 wherein the variable measurable by a change in a capacitor gap is acceleration.

16. The circuit of claim 13 wherein a voltage generating device is a bias circuit for generating bias voltages.

17. The circuit of claim 16 wherein the bias circuit includes four resistors being a first resistor, a second resistor, a third resistor and a fourth resistor, and three operational amplifiers being a second operational amplifier, a third operational amplifier, and a fourth operational amplifier and wherein the second operational amplifier is coupled to a junction between the first and second resistors, wherein the third operational amplifier is coupled to a junction between the second and third resistors, wherein the fourth operational amplifier is coupled to a junction between the third and fourth resistors, wherein the resistors are coupled in series to each other in order of the first resistor, the second resistor, the third resistor and the fourth resistor.

18. The circuit of claim 16 wherein the voltage generating devices include at least one voltage divider and a unity gain buffer.

19. The circuit of claim 13 wherein the timing device is a two-phase nonoverlapping clock.

20. The circuit of claim 13 wherein voltage is the electrical signal output from the inverting output terminal of the operational amplifier and the noninverting output of the operational amplifier, and the voltages are correlated to a change in a variable measurable by change in a capacitor gap.

21. The circuit of claim 13 wherein the substantially constant supply voltages generated by the voltage generating devices are trimmed to account for variations in capacitance for said second capacitor.

22. The circuit of claim 21 wherein the circuit further includes a digital to analog converter that generates a digital to analog converter voltage for trimming substantially constant supply voltages.

23. The circuit of claim 13 wherein a ratio of the sensor capacitance prior to a change in capacitor gap and the capacitance of the reference capacitor is trimmed to account for variations in capacitance for said second capacitor.