Pin electronics interface circuit

• US 20030057990A1
• Filed: 08/09/2002
• Published: 03/27/2003
• Est. Priority Date: 08/17/2001
• Status: Active Grant

• Current Assignee: Xcerra Corporation (COHU Incorporated)
• Original Assignee: Credence Systems Corporation (COHU Incorporated)
• Inventors: West, Burnell G.
• Granted Patent: US 6,940,271 B2
• Time in Patent Office: Days
• US Class Current: 324/765
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

A pin electronics circuit for use in automatic test equipment may include a reconfigurable logic device in which different logic configurations may be installed to make measurements according to multiple tests to be applied to a device under test; a level generating circuit coupled to the reconfigurable logic device, and configured to generate a number of test levels and a number of reference levels; and a switching circuit, coupled to the reconfigurable logic device and the level generating circuit, configured to receive the test levels and the reference levels, and controlled by the reconfigurable logic device to selectively apply the test levels to the device under test according to a selected test and to sense levels inputted to or outputted from the device under test by comparing the reference levels generated by the level generating circuit to the levels inputted to our outputted from the device under test..

Claims

1. A pin electronics circuit for use in automatic test equipment, said circuit comprising:

a plurality of digital-to-analog converters, each capable of generating a test signal or a reference signal;

a plurality of switches, each configured to receive a corresponding one of the test signals;

a plurality of operational amplifiers, each coupled to a corresponding switch, and capable of driving the switches to select a received test signal;

a buffer coupled to the switches, and capable of driving the selected test signal to a device under test; and

a plurality of comparators, each coupled to the device under test and one of the digital-to-analog converters, and configured to receive a reference signal and to compare the received reference signal to a signal applied to or outputted from the device under test.

2. The pin electronics circuit of claim 1 further comprising a non-linear network coupled between the buffer and the device under test.

3. The pin electronics circuit of claim 1 wherein each one of the plurality of switches is a complementary metal oxide semiconducting switch.

4. The pin electronics circuit of claim 1 further comprising a reconfigurable logic device configured to make measurements according to tests to be applied to the device under test.

5. The pin electronics circuit of claim 4, wherein the reconfigurable logic device comprises a field programmable gate array.

6. The pin electronics circuit of claim 4, wherein the reconfigurable logic device comprises a digital test sequencer having a plurality of outputs, each output configured to output a test vector, and a plurality of inputs, each input configured to receive a signal corresponding to an output from one of the plurality of comparators.

7. The pin electronics circuit of claim 6, wherein the reconfigurable logic device further comprises a parametric measurement unit coupled to the plurality of digital to analog converters and capable of setting the test signal and the reference signal to predetermined levels in accordance with a specified test.

8. A pin electronics circuit for use in automatic test equipment, said pin electronics circuit comprising:

a reconfigurable logic device in which different logic configurations may be installed to make measurements according to a plurality of tests to be applied to a device under test;

a level generating circuit coupled to the reconfigurable logic device, and configured to generate a plurality of test levels and a plurality of reference levels; and

a switching circuit, coupled to the reconfigurable logic device and the level generating circuit, configured to receive the plurality of test levels and the plurality of reference levels, and controlled by the reconfigurable logic device to selectively apply the plurality of test levels to the device under test according to the plurality of tests.

9. The pin electronics circuit of claim 8 wherein the switching circuit comprises:

a plurality of switches, each coupled to the level generating circuit to receive one of the plurality of test levels;

a plurality of operational amplifiers, each coupled between the reconfigurable logic device and a corresponding switch, and capable of driving the corresponding switch to relay the received test level;

a buffer coupled between the switches and the device under test, and capable of driving the received test level to the device under test; and

a plurality of comparators, each coupled to the device under test, the level generating circuit and the reconfigurable logic device, and configured to receive a reference level and to sense levels inputted to or outputted from the device under test in response to the plurality of tests.

10. The pin electronics circuit of claim 9, wherein the switching circuit further comprises a non-linear network coupled between the buffer and the device under test.

11. The pin electronics circuit of claim 9 wherein each one of the plurality of switches is a complementary metal oxide semiconducting switch.

12. The pin electronics circuit of claim 8, wherein the reconfigurable logic device comprises a digital test sequencer having a plurality of outputs, each output configured to output a test vector, and a plurality of inputs, each input configured to receive a signal corresponding to an output from a comparator.

13. The pin electronics circuit of claim 12, wherein the reconfigurable logic device further comprises a parametric measurement unit coupled to the level generating circuit and capable of setting the plurality of test levels and the plurality of reference levels according to the plurality of tests.

14. The pin electronics circuit of claim 8, wherein the level generating circuit comprises a plurality of digital-to-analog converters.

15. A pin electronics circuit for use in automatic test equipment, said pin electronics circuit comprising:

a reconfigurable logic device configured to make measurements according to a plurality of tests to be applied to a device under test, the reconfigurable logic device comprising a digital test sequencer having a plurality of outputs, each output configured to output a test vector, and a plurality of inputs, each input configured to receive a signal corresponding to a test result, and a parametric measurement unit capable of receiving a signal corresponding to the test result and setting a plurality of test levels and a plurality of reference levels according to the plurality of tests;

a level generating circuit comprising a plurality of digital-to-analog converters, each coupled to the parametric measurement unit and configured to generate the test levels and the reference levels set by the parametric measurement unit; and

a switching circuit coupled to the reconfigurable logic device and the level generating circuit, and controlled by the reconfigurable logic device to selectively apply the test levels generated by the level generating circuit to the device under test according to the plurality of tests.

16. The pin electronics circuit of claim 15, wherein the switching circuit comprises:

a plurality of switches, each coupled to a corresponding one of the digital-to-analog converters to receive the plurality of test levels;

a plurality of operational amplifiers, each coupled between one of the outputs of the digital test sequencer and a corresponding switch to receive the test vector and drive the corresponding switch to relay one of the test levels generated by the level generating circuit;

a buffer coupled between the plurality of switches and the device under test, and capable of driving the relayed test level to a device under test; and

a plurality of comparators, each coupled between the device under test and reconfigurable logic device, and configured to receive one of the reference levels generated by the level generating circuit and to compare the received reference level to levels inputted to or outputted from the device under test in response to the plurality of tests.

17. The pin electronics circuit of claim 16, wherein the switching circuit further comprises a non-linear network coupled between the buffer and the device under test.

18. The pin electronics circuit of claim 16 wherein each one of the plurality of switches is a complementary metal oxide semiconducting switch.

19. A method of configuring a test system, the method comprising:

providing a test system having a programmable pin electronics circuit;

configuring the test system to be in communication with a device under test; and

programming the pin electronics circuit to implement a selected test from a plurality of tests.

20. The method of claim 19, wherein programming the pin electronics circuit to implement a selected test from a plurality of tests comprises:

setting values for a plurality of test levels and a plurality of reference levels;

generating the plurality of test levels and the plurality of reference levels at the set values; and

applying selectively the generated plurality of test levels to the device under test according to the selected test.

21. The method of claim 20, wherein programming the pin electronics circuit to implement a selected test further comprises sensing levels inputted to or outputted from the device under test in response to the selected test.

22. The method of claim 21, wherein programming the pin electronics circuit to implement a selected test further comprises comparing the sensed levels inputted to or outputted from the device under test in response to the selected test to the reference levels.

23. The method of claim 22, wherein programming the pin electronics circuit to implement a selected test further comprises outputting a signal corresponding to results of the selected test to a display device.

24. A method of claim 23, wherein providing a test system having a programmable pin electronics circuit comprises providing a test system having a plurality of digital test sequencers, a parametric measurement unit, a level generating circuit and a plurality of switching circuits.

25. A method of configuring a test system, the method comprising:

providing a test system having a programmable pin electronics circuit including a plurality of digital test sequencers, a parametric measurement unit, a level generating circuit and a plurality of switching circuits;

configuring the test system to be in communication with a device under test; and

programming the pin electronics circuit to implement a selected test from a plurality of tests.

26. The method of claim 25, wherein programming the pin electronics circuit to implement a selected test comprises:

programming the parametric measurement unit to set values for a plurality of test levels and a plurality of reference levels;

sending the set values for the test levels and the reference levels to the level generating circuit;

programming the level generating circuit to generate the test levels and the reference levels at the set values;

applying the plurality of test levels and the reference levels selectively to the switching circuits;

programming the digital test sequencer to control the switching circuits to selectively apply the plurality of test levels to the device under test according to a plurality of tests.

sensing levels inputted to or outputted from the device under test in response to the plurality of tests; and

comparing the levels inputted to or outputted from the device under test to the reference levels.