Flash memory array structure
First Claim
1. A flash memory device comprising:
- a poly silicon layer having a plurality of word lines formed therein, the word lines are coupled to rows of memory cells;
a first metal layer having a plurality of local bit lines formed therein, the local bit lines are coupled to columns of memory cells; and
a second metal layer having a plurality of global bit lines formed therein, the global bit lines are selectively coupled to the plurality of local bit lines, the global bit lines are further selectively bisected during manufacture to form a first bank and a second bank of memory cells, wherein concurrent memory operations can be performed on the first and second banks.
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Accused Products
Abstract
A flash memory array structure that has independently operating memory arrays. In one embodiment, a flash memory device comprises a poly silicon layer, a first metal layer and a second metal layer. The poly silicon layer has a plurality of word lines formed therein. The word lines are coupled to rows of memory cells. The first metal layer has a plurality of local bit lines formed therein. The local bit lines are coupled to columns of memory cells. The second metal layer has a plurality of global bit lines formed therein. The global bit lines are selectively coupled to the plurality of local bit lines. The global bit lines are further selectively bisected during manufacture to form a first bank and a second bank of memory cells. The first and second banks allow concurrent memory operations to be performed on the flash memory device.
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Citations
43 Claims
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1. A flash memory device comprising:
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a poly silicon layer having a plurality of word lines formed therein, the word lines are coupled to rows of memory cells;
a first metal layer having a plurality of local bit lines formed therein, the local bit lines are coupled to columns of memory cells; and
a second metal layer having a plurality of global bit lines formed therein, the global bit lines are selectively coupled to the plurality of local bit lines, the global bit lines are further selectively bisected during manufacture to form a first bank and a second bank of memory cells, wherein concurrent memory operations can be performed on the first and second banks. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A non-volatile memory device comprising:
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a first and second bank, each bank having a pair of quadrants of non-volatile memory cells, the memory cells in each quadrant are arranged in row and column fashion;
a word line for each row of memory cells in each quadrant, each word line is formed in a poly silicon layer;
a local bit line for each column in each quadrant, each local bit line is formed in a first metal layer; and
a plurality of global bit lines selectively coupled to the local bit lines in each quadrant, the global bit lines are formed in a second metal layer, wherein the global bit lines are disconnected at selected locations to form the first and second bank. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A flash memory device comprising:
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a memory array having memory cells arranged in rows and columns;
a word line for each row of memory cells in the memory array, each word line is formed in a poly silicon layer;
a local bit line for each row of memory cells in the memory array, each local bit line is formed in a first metal layer; and
a plurality of global bit lines selectively coupled to the local bit lines, each global bit line is formed in a second metal layer, wherein the global bit lines are selectively bisected to form a first and second bank of memory cells in the memory array to allow concurrent memory operations. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method of forming a flash memory device having a pair of independently operating memory arrays comprising:
bisecting global bit lines at predetermined locations during manufacture of the flash memory device to form independently operating memory arrays. - View Dependent Claims (28, 29, 30, 31)
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32. A method of forming a flash memory device comprising:
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forming word lines in a poly silicon layer;
forming local bit lines in a first metal layer;
forming global bit lines in a second metal layer, wherein the first metal layer is positioned between the poly silicon layer and the second metal layer; and
masking the second metal layer while the global bit lines are being formed to break the global bit lines at desired locations, wherein a first and second bank of memory cells in the flash memory device is formed. - View Dependent Claims (33, 34, 35)
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36. A method of forming a flash memory device comprising:
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forming word lines in a poly silicon layer, wherein the word lines are coupled to gates of memory cells arranged in columns in a memory array;
forming local bit lines in a first metal layer, wherein the local bit lines are coupled to drains of memory cells arranged in rows in the memory array;
forming global bit lines in a second metal layer, wherein the global bit lines are selectively coupled to the local bit lines; and
bisecting the global bit lines at predetermined locations to form a first and second bank in the memory array, wherein concurrent memory operations can be performed on the first and second banks. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43)
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Specification