Hybrid architecture for realizing a random numbers generator

• US 20030059046A1
• Filed: 07/18/2002
• Published: 03/27/2003
• Est. Priority Date: 07/20/2001
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Polizzi, Salvatore, Messina, Marco, Mangione, Giulio
• Granted Patent: US 7,139,397 B2
• Time in Patent Office: Days
• US Class Current: 380/46
• CPC Class Codes: H04L 2209/12 Details relating to cryptographic hardware or logic circuitry
• CPC Class Codes: H04L 2209/26 Testing cryptographic entity, e.g. testing integrity of encryption key or encryption algorithm
• CPC Class Codes: H04L 9/0662 with particular pseudorandom sequence generator

Abstract

A hybrid architecture for realizing a random numbers generator comprising a digital circuitry portion able to provide for a random bytes sequence as well as an analog circuitry portion able to provide a seed of the true random type is described.

Claims

1. A hybrid architecture for realizing a random numbers generator, comprising a digital circuitry portion, able to provide for a random bytes sequence, and an analog circuitry portion coupled to the digital circuitry portion and able to provide a true random seed.

2. The hybrid architecture of claim 1, wherein the analog circuitry portion comprises a thermal noise amplifier.

3. The hybrid architecture of claim 2, wherein the thermal noise amplifier is digitalized.

4. The hybrid architecture of claim 3, wherein the thermal noise amplifier provides an output bit stream to the digital circuitry portion.

5. The hybrid architecture of claim 2, wherein the thermal noise amplifier furnishes a square-wave signal starting from an amplified thermal noise, and the analog circuitry portion includes a shift register that is charged by the square-wave signal.

6. The hybrid architecture of claim 1, wherein the analog circuitry portion includes an output bus connected to the digital circuitry portion.

7. The hybrid architecture of claim 6, wherein the digital circuitry portion comprises:

a plurality of linear feedback shift registers connected to the output bus of the analog circuitry portion; and

a clock generator comprising a plurality of clock oscillators structured to provide an irregular clock signal to the linear feedback shift registers.

8. The hybrid architecture of claim 7, wherein the digital circuitry portion further comprises a scrambling device inserted between first and second registers of the plurality of linear feedback shift registers, the scrambling device being in turn connected to the output bus of the analog circuitry portion.

9. The hybrid architecture of claim 7, wherein at least one of the plurality of clock oscillators of the clock generator is in turn connected to the output bus of the analog circuitry portion.

10. The hybrid architecture of claim 9, wherein the at least one of the plurality of clock oscillators comprises a switch connected to the output bus of the analog circuitry portion.

11. A random numbers generator comprising:

a digital circuitry portion;

an analog circuitry portion; and

a bus connecting the analog circuitry portion to the digital circuitry portion.

12. The generator of claim 11, wherein the analog circuitry portion comprises a digitalized thermal noise amplifier providing an output bit stream.

13. The generator of claim 12, wherein the analog circuitry portion furnishes a square-wave signal starting from an amplified thermal noise, the square-wave signal being used to charge a shift register within the analog circuitry portion.

14. The generator of claim 11, wherein the digital circuitry portion comprises:

a plurality of linear feedback shift registers connected to the bus; and

a clock generator in turn comprising a plurality of clock oscillators structured to provide an irregular clock signal to the linear feedback shift registers.

15. The generator of claim 14, wherein the digital circuitry portion further comprises a scrambling device inserted between first and second registers of the plurality of linear feedback shift registers, the scrambling device being in turn connected to the bus.

16. The generator of claim 14, wherein at least one of the plurality of clock oscillators of the clock generator is in turn connected to the bus.

17. The generator of claim 14, wherein the at least one of the plurality of clock oscillators comprises a switch connected to the bus.

18. Method for generating a random number comprising the following phases:

providing a first random sequence by means of an analog circuitry portion of a random numbers generator; and

providing a random number by means of a digital circuitry portion of a random numbers generator using the first random sequence as starting sequence.

19. The method of claim 18, wherein said phase of providing a random number by means of the digital circuitry portion of the random numbers generator comprises a phase of changing of frequencies of a plurality of clock oscillators comprised in the digital circuitry portion in function of said first random sequence obtained by means of the analog circuitry portion of the random numbers generator.

20. The method of claim 18, wherein said phase of providing a random number by means of the digital circuitry portion of the random numbers generator comprises a phase of triggering the speed of a plurality of linear feedback shift registers comprised in the digital circuitry portion in function of said first random sequence obtained by means of the analog circuitry portion of the random numbers generator.

21. The method of claim 18, wherein said phase of providing a random number by means of the digital circuitry portion of the random numbers generator comprises a phase of changing the logic of a scrambling device comprised in the digital circuitry portion in function of said first random sequence obtained by means of the analog circuitry portion of the random numbers generator.