Integrated package and methods for making same

• US 20030059976A1
• Filed: 03/12/2002
• Published: 03/27/2003
• Est. Priority Date: 09/24/2001
• Status: Abandoned Application

• Current Assignee: Richard J. Nathan, William H. Shepherd
• Original Assignee: Richard J. Nathan, William H. Shepherd
• Inventors: Nathan, Richard J., Shepherd, William H.
• Application Number:
  US10/098,021
• Publication Number:
  US 20030059976A1
• Time in Patent Office: Days
• US Class Current: 438/106
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/82001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/82103 using laser direct writing
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10157 : at the active surface
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

One or more integrated circuit chips each containing conductive pads on one surface, are embedded in a substrate such that the conductive pads are exposed and the one surface of each chip is substantially coplanar with a top surface of the substrate. Electrically conductive material is placed over the one surface, including conductive pads, of each chip and the top surface of the substrate and patterned, using standard semiconductor or printed circuit photolithographic and processing techniques to form an electrically conductive interconnect pattern connecting the one or more integrated circuit chips into an electronic system. When a single integrated circuit chip is to be embedded in a substrate, the invention makes possible the simultaneous manufacture of a plurality of such packaged integrated circuit chips in a single large substrate using standard semiconductor or printed circuit photolithographic and processing techniques and then singulating the large substrate into a plurality of smaller substrates, each containing a single integrated circuit chip. Likewise, when more than one integrated circuit chip is embedded in a substrate, a plurality of such structures can be manufactured in a single large substrate and then singulated into a plurality of smaller substrates, each containing more than one integrated circuit chip. A plurality of substrates with embedded integrated circuit chips can be stacked to form a composite multichip, multi-layered structure. Additional chips, packaged or unpackaged, can be placed on the top of this composite structure.

Claims

1. A structure comprising:

a substrate having a top surface; and

at least one semiconductor integrated circuit embedded in said substrate, each of said at least one semiconductor integrated circuit containing conductive pads on one surface thereof, each of said at least one semiconductor integrated circuit being embedded in said substrate such that the conductive pads on the integrated circuit face outward and are visible along with said top surface.

2. Structure as in claim 1 wherein said one surface on each of said at least one semiconductor integrated circuit is substantially coplanar with said top surface.

3. Structure as in claim 1 including:

a layer of conductive material formed over said one surface of said at least one semiconductor integrated circuit and over the top surface of said substrate, said layer of conductive material being patterned to form an electrically conductive interconnect structure interconnecting the conductive pads on said one surface of said at least one semiconductor integrated circuit so as to form a desired electronic circuit.

4. Structure as in claim 3 wherein at least one cavity is formed in said substrate and wherein each of said at least one semiconductor integrated circuit is placed in a corresponding cavity formed in said substrate.

5. Structure as in claim 4 wherein each cavity is of approximately the same lateral dimensions as the lateral dimensions of the integrated circuit placed in the cavity.

6. Structure as in claim 4 including a passivating layer formed over the one surface of each of the at least one semiconductor integrated circuit and over the top surface of said substrate.

7. Structure as in claim 4 wherein each of said at least one semiconductor integrated circuit is held in a cavity in said substrate by means of an adhesive material.

8. Structure as in claim 7 wherein said adhesive material comprises glue.

9. Structure as in claim 7 wherein said adhesive material comprises epoxy.

10. Structure as in claim 4 wherein each cavity in the substrate has tapered sides.

11. Structure as in claim 10 wherein the angle of the taper of each tapered side with the vertical is in the range between 0°

to about plus or minus 45°

from vertical.

12. Structure as in claim 11 wherein each integrated circuit to be placed in a corresponding cavity has tapered sides, and wherein each of the tapered sides of said at least one semiconductor integrated circuit substantially matches the tapers on the sides of the cavity in which said at least one semiconductor integrated circuit is placed.

87. Structure as claim 1 wherein said at least one semiconductor is formed of a semiconductor material selected from the group consisting of silicon, germanium, gallium-arsenide and a combination thereof.

13. The method of fabricating a packaged semiconductor chip which comprises:

providing a substrate;

forming a cavity in said substrate, said cavity having the lateral dimensions of an integrated circuit chip to be placed in said cavity;

placing an integrated circuit chip in said cavity, said integrated circuit chip having lateral dimensions substantially the same as those of the cavity, and having a top surface containing thereon electrically conductive pads for use in electrically contacting the circuitry formed in said integrated circuit chip, said pads on the surface of said integrated circuit chip being visible in said cavity;

forming a layer of conductive material over the top surface of said integrated circuit chip, said electrically conductive pads and the top surface of said substrate; and

forming said electrically conductive material into an electrically conductive interconnect pattern selectively interconnecting said pads to form an electrical circuit.

14. The method of claim 13 wherein the exposed surface of said integrated circuit chip is substantially coplanar with the top surface of said substrate.

15. The method of claim 13 wherein said substrate is formed of a heat sensitive material which softens under increased pressure and temperature thereby to allow said integrated circuit chip to be pressed into the softened material of said substrate.

16. The method of claim 15 including the steps of:

heating said substrate to soften the material making up said substrate;

pressing on said integrated circuit chip to press said integrated circuit chip into the softened substrate material until the top surface of said integrated circuit chip is approximately coplanar with the top surface of said substrate; and

allowing the substrate to cool thereby to adherently embed the integrated circuit chip into said substrate.

17. The method of fabricating a monolithic integrated structure containing one or more integrated circuit chips embedded in a substrate comprising:

placing the one or more integrated circuit chips to be embedded in said substrate in a template;

pressing the template against the top surface of the substrate in which the one or more integrated circuit chips are to be embedded;

heating the substrate so as to soften the material making up the substrate;

pressing the one or more integrated circuit chips placed on the top surface of said substrate into the softened material of the substrate using a planarizing plate until the top surfaces of said one or more integrated circuit chips are substantially coplanar with the top surface of said substrate; and

allowing the substrate containing the one or more integrated circuit chips to cool.

18. The method of claim 17 including the additional steps of

forming a conductive layer over the top surfaces of said one or more integrated circuit chips and the top surface of said substrate;

and

patterning the conductive layer to form an electrically conductive interconnect structure which interconnects the one or more integrated circuit chips formed in said substrate into a desired electronic system.

19. The method of claim 18 including:

mounting said one or more integrated circuit chips in said template such that the surface of each of the one or more integrated circuit chips which contains conductive pads faces the substrate in which the one or more integrated circuit chips are to be embedded;

placing the one or more integrated circuit chips on the surface of said substrate using said template;

embedding said one or more integrated circuit chips into said substrate by heating the substrate to soften the substrate material and pressing on said integrated circuit chips until the top surface of each of said one or more integrated circuit chips containing the pads has penetrated through the softened substrate material to a planarizing plate on the opposite surface of said substrate; and

allowing the substrate to cool.

20. The method of claim 19 including:

placing on said opposite surface of said substrate conductive material in electrical contact with the pads on the surface of each of said one or more integrated circuit chips; and

forming the conductive material into an electrically conductive interconnect pattern to interconnect the one or more integrated circuit chips in said substrate into a desired electrical circuit.

21. The method of claim 20 including:

applying a prepreg layer to the back surfaces of said one or more integrated circuit chips and said substrate thereby to seal said one or more integrated circuit chips in said substrate.

22. Structure comprising:

a substrate having a top surface;

at least one cavity formed in said substrate adjacent said top surface; and

at least one integrated circuit chip placed in said at least one cavity so that each of said at least one integrated circuit chip has a visible surface approximately coplanar with the top surface of said substrate.

23. Structure as in claim 22 wherein each of said at least one integrated circuit chip includes a plurality of electrically conductive pads formed on said visible surface.

24. Structure as in claim 23 including a conductive layer formed over the visible surface of each of said at least one integrated circuit chip, said plurality of electrically conductive pads and the top surface of said substrate.

25. Structure as in claim 24 including conductive traces formed on the top surface of said substrate.

26. Structure as in claim 25 wherein said conductive layer is patterned to form a plurality of conductive leads interconnecting selected ones of the pads on each of said at least one integrated circuit chip to selected ones of said conductive traces.

27. Structure as in claim 26 wherein said substrate comprises a printed circuit board and said conductive traces on said printed circuit board interconnect each of said at least one integrated circuit chip with other integrated circuit chips similarly placed on said printed circuit board.

28. Structure as in claim 22 wherein said substrate contains a plurality of cavities, each of said plurality of cavities containing a corresponding integrated circuit chip.

29. Structure as in claim 28 wherein each of said corresponding integrated circuit chips has a visible surface approximately coplanar with the top surface of said substrate.

30. Structure as in claim 28 wherein each of said integrated circuit chips has a plurality of electrically conductive pads formed on its visible surface.

31. Structure as in claim 30 wherein said plurality of electrically conductive pads formed on the visible surface of each of said integrated circuit chips allows electrical connection to electrical circuitry contained in each of said integrated circuit chips.

34. The structure as in claim 22 wherein each of said cavities has tapered sides.

35. Structure as in claim 22 where each of said cavities has substantially vertical sides.

36. Structure as in claim 22 wherein the substrate is formed of a material from the group consisting of plastic, ceramic, epoxy and any combination thereof.

37. Structure as in claim 24 wherein the conductive layer comprises a metal selected from the group consisting of copper, aluminum, and a composite of copper and aluminum.

38. Structure as in claim 24 wherein said conductive layer comprises copper.

39. Structure as in claim 24 wherein said conductive layer comprises a conductive metal.

40. Structure as in claim 24 wherein said conductive layer comprises a composite layer comprised of copper laminated with a prepreg.

41. Structure as in claim 22 wherein said substrate is formed of multiple layers of conductive material formed into conductive traces and dielectric material.

42. Structure as in claim 41 wherein said substrate includes at least one electrically conductive layer formed on one surface thereof.

43. Structure as in claim 42 wherein said substrate includes a conductive plane formed below at least one of said at least one cavity.

44. Structure as in claim 43 wherein the conductive plane can be used as either a ground plane, a VCC plane or an RF shield.

45. Structure as in claim 43 wherein said conductive plane comprises a ground plane.

46. Structure as in claim 43 wherein said conductive plane comprises a VCC plane.

47. Structure as in claim 22 wherein said at least one integrated circuit chip placed in said at least one cavity has a first face upon which are formed electrically conductive pads and a second face with no conductive pads, and said at least one integrated circuit chip is placed in said at least one cavity such that the conductive pads face up and are in a plane approximately coplanar with the top surface of said substrate.

48. Structure as in claim 22 wherein each of said at least one integrated circuit chip has pads on one face and no pads on a second face and is placed into said at least one cavity such that the pads face the bottom of the cavity.

49. Structure as in claim 22 wherein each of said at least one cavity has sidewalls that are substantially perpendicular to said top surface.

50. Structure as in claim 22 wherein each of said at least one cavity has sidewalls which are angled with respect to the top surface.

51. Structure as in claim 22 wherein each of said at least one integrated circuit chip has sidewalls which form an angle with said top surface, said angle being different from the angle formed by the sidewalls of each of said at least one cavity with said top surface.

52. Structure as in claim 24 wherein said conductive layer formed over the visible surface of each of said at least one integrated circuit chip and the top surface of said substrate is formed at least in part by a process selected from the processes consisting of plating, sputtering, evaporation, and direct laser writing.

53. Structure as in claim 22 wherein each of said at least one integrated circuit chip is held in its cavity by an adhesive, prepreg or plastic such that said at least one integrated circuit chip is permanently attached in its cavity.

54. Structure as in claim 22 wherein each of said at least one integrated circuit chip is held in its cavity by an adhesive which forms a temporary bond between said integrated circuit chip and the cavity thereby to allow the removal and/or replacement of the integrated circuit chip from its matching cavity.

55. Structure as in claim 24 wherein said conductive layer is patterned to form an electrically conductive interconnect to carry electrical signals between each of said at least one integrated circuit chip and traces on the substrate, thereby to form an electrical system.

56. A plurality of structures, each structure comprising the structure as set forth in claim 22, said plurality of structures being stacked such that each such structure but one is on top of another such structure such that said plurality of structures thereby form a multilayer composite structure.

57. Structure as in claim 22 wherein conductive vias are formed in said substrate thereby to electrically interconnect multiple layers of conductive traces in said substrate.

58. Structure as in claim 24 wherein said conductive layer is formed from a conductive epoxy or other conductive non-metallic material and is formed into an electrical interconnect pattern.

80. Structure as in claim 22 wherein said substrate comprises a plastic including fibers selected from the group consisting of glass, fiber glass, and aramid materials.

81. Structure as in claim 22 wherein said substrate comprises a metal stamped to form said at least one cavity.

82. Structure as in claim 22 wherein said substrate comprises a prepreg laminate material.

83. Structure as in claim 22 wherein said substrate comprises a ceramic.

84. Structure as in claim 22 wherein said substrate comprises a prepreg laminate material molded to form said at least one cavity in said substrate.

85. Structure as in claim 22 wherein said at least one cavity has a bottom and an opening in said top surface with the dimensions of said opening being larger than the dimensions of said bottom

86. Structure as in claim 22 wherein said at least one cavity has a bottom and an opening in said top surface with the dimensions of said opening being smaller than the dimensions of said bottom.

88. Structure as in claim 24 wherein part or all of the conductive layer is formed by a process called direct laser write.

89. Structure as in claim 26 wherein part of all of said conductive layer is formed by a direct laser write process.

91. Structure as in claim 24 wherein the structure is a single or multi-layer laminate with part or all of the electrical traces and routes completed and tested prior to inserting the die.

92. Structure as in claim 24 wherein the structure is a multi-layer laminate with part or all of the electrical traces and electrically conductive interconnects completed and tested prior to inserting the die into the structure.

95. Structure as in claim 24 wherein part or all of the conductive layer is formed by a process called direct laser write.

96. Structure as in claim 43 wherein said conductive plane comprises an RF shield.

97. Structure as in claim 96 wherein said conductive plane is a continuous layer of conductive material.

98. Structure as in claim 96 wherein said conductive plane is a mesh of conductive material.

32. The method of fabricating a substrate having a top surface which comprises:

forming a plurality of cavities in said substrate, each said cavity having an opening in said top surface;

placing a corresponding plurality of integrated circuit chips in said plurality of cavities such that a visible surface of each of said integrated circuit chips is substantially coplanar with said top surface, each of said integrated circuit chips having a plurality of electrically conductive pads formed on its visible surface;

forming a conductive layer on the top surface of said substrate, on the visible surfaces of said integrated circuit chips and on the plurality of conductive pads on each visible surface; and

patterning the conductive layer to form a conductive interconnect to interconnect the integrated circuit chips into a desired circuit.

33. The method of claim 32 wherein said step of patterning the conductive layer comprises:

forming a photoresist material on said conductive layer;

removing selected portions of said photoresist to expose portions of said conductive layer to be removed from said structure; and

removing exposed portions of the conductive layer from the structure so as to leave said conductive interconnect.

90. The method of claim 32 wherein forming said conductive layer comprises forming said conductive layer using a direct laser write process.

93. The method of claim 32 including testing the conductive interconnect used to interconnect the integrated circuit chips into a desired circuit prior to placing the plurality of integrated circuit chips into the corresponding plurality of cavities.

94. The method of claim 32 wherein said substrate comprises a multi-layer laminate.

59. A structure made of thermoplastic or thermo-set plastic or a composite thereof, comprising:

a substrate having a top surface;

at least one cavity formed in said substrate, said cavity having lateral dimensions representative of the lateral dimensions of an integrated circuit chip to be placed in said cavity;

an integrated circuit chip placed in one of said at least one cavity such that one surface of said integrated circuit chip is approximately co-planar with the top surface of said substrate; and

an electrically conductive layer formed over the top surface of said substrate and the approximately co-planar one surface of said integrated circuit chip.

60. Structure as in claim 59 having the characteristic that when said thermoplastic or thermo-set plastic is heated and softens, the thermoplastic or thermo-set plastic will flow around and adherently contact the integrated circuit chip to form plastic material in any cavity that may exist between the sides of the integrated circuit chip and the sides of the cavity in which the integrated circuit chip is placed thereby to adherently hold the integrated circuit chip in the cavity.

61. The method of fabricating a structure containing a plurality of integrated circuit chips which comprises:

placing a plurality of integrated circuit chips in a template, each integrated circuit chip having one surface directly adjacent said template upon which has been formed a plurality of electrically conductive pads;

placing said template adjacent a substrate of heat-softenable material such that the surface of each integrated circuit chip opposite said one surface is in contact with said substrate;

heating said substrate so as to allow each integrated circuit chip to adhere to said substrate;

removing said template and placing a planarizing plate adjacent the surfaces of said integrated circuit chips containing said electrically conductive pads;

heating said substrate so as to soften the material of said substrate; and

using the planarizing plate to press said integrated circuit chips into the softened material of said substrate until the top surface of each of the integrated circuit chips is approximately coplanar with the top surface of said substrate thereby to create an embedded structure.

62. The method of claim 61 including:

cooling said substrate thereby to allow the material of said substrate to harden and thus firmly embed the integrated circuit chips in said substrate.

63. The method of claim 62 wherein said planarizing plate has a coating of material formed on the surface of said planarizing plate in contact with said integrated circuit chips to allow said planarizing plate to be easily removed from contact with said integrated circuit chips.

100. The method of claim 61 including placing a polymer or other plastic over the surface of each integrated circuit chip to protect the surface of each chip while creating said embedded structure.

101. The method of claim 61 including placing a temporary coating such as a polymer or other plastic having a controlled thickness over the top surface of each of said plurality of integrated circuit chips to purposely embed each of said integrated circuit chips said controlled thickness below said top surface of the substrate.

102. The method of claim 101 including removing the temporary coating using solvents, chemical etching or plasma to expose the previously covered surfaces of the integrated circuit chips.

64. The method of fabricating a monolithic integrated structure containing a plurality of integrated circuit chips which comprises:

placing the plurality of integrated circuit chips adjacent a planarizing plate;

causing said integrated circuit chips to attach to said planarizing plate;

placing said planarizing plate with said integrated circuit chips attached thereto into an injection mold; and

injecting plastic material into said injection mold such that said plastic material surrounds each of said integrated circuit chips thereby to form an integrated structure holding each of said integrated circuit chips in fixed relationship to each other.

65. The method of claim 64 wherein each of said integrated circuit chips has a plurality of electrically conductive pads formed on one surface thereof directly adjacent the planarizing plate.

66. The method of claim 65 including:

removing the injection molded structure from the injection mold;

removing the planarizing plate from the injection molded structure; and

forming an electrically conductive layer of material over the conductive pads and on the exposed surfaces of said integrated circuit chips and the top surface of said plastic material formed by injection molding.

67. The method of claim 66 including patterning said conductive layer into an electrically conductive interconnect so as to form said integrated circuit chips into a desired electrical circuit or system.

99. The method or claim 66 wherein part or all of said electrically conductive layer is formed by a direct laser write process

68. The method of fabricating a monolithic integrated structure containing one or more integrated circuit chips, which comprises:

providing a substrate;

picking one or more integrated circuit chips from a source of said integrated circuit chips and placing each of said one or more integrated circuit chips in a corresponding location on said substrate such that each said integrated circuit chip so placed is properly oriented in accordance with a planned orientation; and

causing each said integrated circuit chip to be adherently held in position on said substrate.

69. The method of claim 68 including:

heating said substrate so as to soften the material of said substrate;

pressing each of said integrated circuit chips into the softened material of such substrate such that the top surface of each of said integrated circuit chips is visible but substantially coplanar with the top surface of said substrate; and

allowing the substrate to cool, thereby to solidly embed each of said integrated circuit chips in said cooled substrate.

70. The method of claim 69 including:

forming a layer of conductive material over the top surfaces of each of said integrated circuit chips and over the top surface of said substrate; and

patterning said conductive material into a selective electrically conductive interconnect pattern, thereby to interconnect said integrated circuit chips into a desired electrical circuit or system.

71. The method of fabricating a monolithic integrated structure containing one or more integrated circuit chips which comprises:

providing a substrate having a top surface thereon;

providing a template with openings in one surface thereof for receipt of one or more integrated circuit chips;

picking one or more integrated circuit chips from a source of such integrated circuit chips and placing each of said one or more integrated circuit chips in a corresponding opening in said template such that each said integrated circuit chip so placed is properly oriented in accordance with a planned orientation; and

placing said template adjacent said substrate such that the one or more integrated circuit chips in said template are placed in corresponding locations on said substrate.

72. The method of claim 71 including:

applying adhesive to the top surface of said substrate; and

pressing the one or more integrated circuit chips held by said template against said adhesive thereby to cause said one or more integrated circuit chips to be held in the proper orientation on the top surface of said substrate.

73. The method of claim 71 including:

heating said substrate such that said top surface becomes tacky; and

pressing the one or more package components held by said template against said tacky top surface thereby to cause said one or more integrated circuit chips to be held in the proper orientation on said top surface.

74. The method of claim 72 including:

removing said template from said substrate while leaving the one or more integrated circuit chips in proper location on said substrate.

75. The method of fabricating a monolithic integrated structure containing one or more integrated circuit chips which comprises:

providing a substrate having a top surface;

providing one or more cavities in said substrate, said one or more cavities opening to said top surface;

providing a source of one or more integrated circuit chips;

picking and placing selected ones of said one or more integrated circuit chips from said source into corresponding ones of said one or more cavities; and

causing said one or more integrated circuit chips to be firmly held in said one or more cavities.

76. The method of claim 75 including:

placing an adhesive on the bottom surfaces of said one or more cavities so as to hold the corresponding one or more integrated circuit chips in said cavities.

77. The method of claim 76 including:

placing each of said one or more integrated circuit chips in said one or more cavities such that electrically conductive pads on a surface of each of said one or more integrated circuit chips are visible along with the top surface of said substrate.

78. The method of claim 77 including:

providing one or more cavities in said substrate of such a depth that the one or more integrated circuit chips placed in said one or more cavities each have a visible surface approximately coplanar with the top surface of said substrate.

79. The method of claim 78 wherein each visible surface of said one or more integrated circuit chips includes thereon a plurality of electrically conductive pads for making electrical contact with the electrical component within the corresponding integrated circuit chip, and the method includes:

forming an electrically conductive layer on the top surface of said substrate, on the visible surface or surfaces of the one or more integrated circuit chips and on the electrically conductive pads on each of said visible surfaces; and

patterning said electrically conductive layer into an electrically conductive interconnect structure to interconnect the one or more integrated circuit chips to form a desired electrical circuit or system.

103. A module comprising;

a plurality of substrates, each substrate having a top surface; and

a plurality of integrated circuit die, each die being embedded in a corresponding substrate of a heat deformable material to form a structure such that the top surface of each said die is substantially coplanar with the top surface of the substrate in which it is placed, at least two such substrates being arranged one on top of the other.

104. A module as in claim 103, wherein each of said plurality of substrates with an embedded die is joined to the adjacent substrate or substrates by a bond between the substrate material formed by heating each substrate while pressed against the adjacent substrate until the material of each substrate becomes slightly tacky, thereby to allow each substrate to adhere to the adjacent substrate upon cooling.

105. A module as in claim 103, including a plurality of electrically conductive balls formed on a first surface thereof to allow electrical signals to be sent to and received from the integrated circuit chips contained within the module.

106. A module as in claim 105, including at least one additional integrated circuit die placed on a second surface of the module opposite said first surface.

107. A module as in claim 106, including at least one additional integrated circuit in a package or electrical component in a package placed on said second surface.

108. A module as in claim 107 wherein said package is a ball grid array package.

109. A module as in claim 108 wherein said ball grid array package is in electrical contact with conductive traces formed on said second surface.

110. A module as in claim 103 including electrical contacts formed on a first surface thereof and at least one electrical component mounted on a second surface thereof.

111. A module in claim 110 wherein said at least one electrical component comprises at least one integrated circuit.

112. A module as in claim 111 wherein said at least one integrated circuit comprises at least one packaged integrated circuit and at least one unpackaged integrated circuit both mounted on said second surface of said module.

113. Structure comprising:

a substrate having a top surface;

at least one integrated circuit chip embedded in said substrate so that said at least one integrated circuit chip has a visible surface approximately coplanar with the top surface of said substrate; and

a conductive plane formed in said substrate beneath said at least one integrated circuit chip, said conductive plane being capable of functioning as a ground plane, Vcc or RF shield.

114. The structure as in claim 113 wherein said conductive plane comprises a solid sheet of conductive material.

115. The structure as in claim 113 wherein said conductive plane is capable of functioning as an RF shield.

116. The structure as in claim 113 wherein said conductive plane extends the full lateral extent of the substrate.

117. The structure as in claim 113 wherein said conductive plane comprises an intertwined mesh of conductive material.

118. The structure as in claim 113 wherein said conductive plane is formed of a meshed construction of conductive material selected from a group consisting of metal, conductive silicide and conductive polymers.