Method of manufacturing semiconductor device with offset sidewall structure
First Claim
1. A method of manufacturing a semiconductor device comprising the steps of:
- (a) sectioning a major surface of a semiconductor substrate into at least a first NMOS region for forming a first NMOS transistor and a first PMOS region for forming a first PMOS transistor;
(b) selectively forming a first gate insulating film in both said first NMOS region and said first PMOS region to form a first gate electrode and a second gate electrode on said first gate insulating film in said first NMOS region and said first PMOS region, respectively; and
(c) ion implanting an N-type impurity using at least said first gate electrode as part of an implant mask to form a pair of first extension layers in the surface of said semiconductor substrate outside a side surface of said first gate electrode, and ion implanting a P-type impurity using at least said second gate electrode as part of an implant mask to form a pair of second extension layers in the surface of said semiconductor substrate outside a side surface of said second gate electrode, said step (c) including the step of;
(c-1) forming first ion-implanted layers by ion implantation of said N-type impurity and second ion-implanted layers by ion implantation of said P-type impurity so that a spacing between said second ion-implanted layers is wider than a spacing between said first ion-implanted layers.
6 Assignments
0 Petitions
Accused Products
Abstract
A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).
-
Citations
6 Claims
-
1. A method of manufacturing a semiconductor device comprising the steps of:
-
(a) sectioning a major surface of a semiconductor substrate into at least a first NMOS region for forming a first NMOS transistor and a first PMOS region for forming a first PMOS transistor;
(b) selectively forming a first gate insulating film in both said first NMOS region and said first PMOS region to form a first gate electrode and a second gate electrode on said first gate insulating film in said first NMOS region and said first PMOS region, respectively; and
(c) ion implanting an N-type impurity using at least said first gate electrode as part of an implant mask to form a pair of first extension layers in the surface of said semiconductor substrate outside a side surface of said first gate electrode, and ion implanting a P-type impurity using at least said second gate electrode as part of an implant mask to form a pair of second extension layers in the surface of said semiconductor substrate outside a side surface of said second gate electrode, said step (c) including the step of;
(c-1) forming first ion-implanted layers by ion implantation of said N-type impurity and second ion-implanted layers by ion implantation of said P-type impurity so that a spacing between said second ion-implanted layers is wider than a spacing between said first ion-implanted layers. - View Dependent Claims (2, 3, 4, 5, 6)
-
Specification