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Method of fabricating a high-voltage transistor with a multi-layered extended drain structure

  • US 20030060001A1
  • Filed: 10/22/2002
  • Published: 03/27/2003
  • Est. Priority Date: 09/07/2001
  • Status: Active Grant
First Claim
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1. A method for fabricating an extended drain region of a high-voltage transistor comprising:

  • forming an epitaxial layer on a substrate, the epitaxial layer being of a first conductivity type and having a top surface;

    etching the epitaxial layer to form a pair of spaced-apart trenches that define a mesa with first and second sidewall portions;

    forming a dielectric layer in each of the trenches, the dielectric layer partially filling each of the trenches and covering the first and second sidewall portions;

    filling a remaining portion of the trenches with a conductive material to form first and second field plate members that are insulated from the substrate and the epitaxial layer.

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