Method of transferring ultra-thin substrates and application of the method to the manufacture of a multi-layer thin film device

• US 20030060034A1
• Filed: 07/25/2002
• Published: 03/27/2003
• Est. Priority Date: 04/02/1999
• Status: Active Grant

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: IMEC VZW A Research Center In The Country of Belgium
• Inventors: Beyne, Eric, Vendier, Olivier, Coello-Vera, Augustin
• Granted Patent: US 6,730,997 B2
• Time in Patent Office: Days
• US Class Current: 438/618
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

The present invention provides a method of transfer of a first planar substrate with two major surfaces to a second substrate, comprising the steps of forming the first planar substrate, attaching one of the major surfaces of the first planar substrate to a carrier by means of a release layer attaching the other major surface of the first substrate to the second substrate with a curable polymer adhesive layer partly curing the polymer adhesive layer, disconnecting the release layer from the first substrate to separate the first substrate from the carrier, followed by curing the polymer adhesive layer.

The method may be used to form a stack of dies (4, 14 . . . ) which are adhered together by cured polymeric layers (7, 17). Each die (4, 14 . . . ) may include a device layer and an ultra-thin substrate manufactured and assembled by the method described above.

Claims

1. A multi-layer thin film device comprising:

a plurality of layers, each layer including a planar three-dimensional interconnect portion having “

X”

, “

Y” and

“

Z”

connection routings and adjacent thereto a planar semiconductor device portion, the semiconductor device portion being connected to the interconnect portion in each layer, the “

X” and

“

Y”

routings lying in the plane of the interconnect portion and the “

Z”

routing being perpendicular thereto, the “

Z”

routing in each interconnect portion being selectably distributed throughout the interconnect portion.

2. The multi-layer thin film device according to claim 1, wherein a Z-routing in one layer is positioned independently of a Z-routing in a layer above or below the one layer.

3. The multi-layer thin film device according to claim 2, wherein the Z-routing in the one layer is a conductive stud which only extends through substantially the complete thickness of the one layer.

4. The multi-layer thin film device according to claim 1, wherein the thickness of each layer is 300 microns or less, preferably 150 microns or less, more preferably 100 microns or less and most preferably 50 microns or less.

5. The multi-layer thin film device according to claim 3, wherein the thickness of each layer is 300 microns or less, preferably 150 microns or less, more preferably 100 microns or less and most preferably 50 microns or less.

6. A method of forming a multi-layer thin film device comprising the steps of:

step 1;

attaching a semiconductor device to a substrate;

step 2;

providing a planar three-dimensional interconnect portion on the substrate having “

X”

, “

Y” and

“

Z”

connection routings adjacent to the semiconductor device, the semiconductor device being connected to the interconnect portion, the “

X” and

“

Y”

routings lying in the plane of the interconnect portion and the “

Z”

routing being perpendicular thereto, the “

Z”

routing in each interconnect portion being selectably distributed throughout the interconnect portion; and

repeating steps 1 and 2 for each layer.

7. The method according to claim 6, wherein a Z-routing in one layer is positioned independently of a Z-routing in a layer above or below the one layer.

8. The multi-layer thin film device according to claim 7, wherein the step of forming the Z-routing in the one layer, includes:

forming a conductive stud which extends only through substantially the complete thickness of the one layer.

9. A multi-layer thin film device comprising:

a plurality of layers forming a stack of layers, each layer including a planar semiconductor device portion on an ultra-thin substrate, the planar semiconductor device portion having a metallisation layer, each layer of the stack being adhered to the next layer by a cross-linked polymeric adhesive layer;

a groove within the stack, the metallisation layer of each semiconductor device portion being exposed in said groove and at least a portion of the metallisation layer extending into the groove.

10. The multi-layer thin film device according to claim 9 which is a memory.