Electronic control unit for vehicle having operation monitoring function and fail-safe function
First Claim
1. An electronic control unit for a vehicle comprising:
- a CPU having a predetermined fail-safe function required after occurrence of a fault in addition to a vehicle operation control;
a monitor circuit for receiving as an input from the CPU a watchdog pulse generated in a predetermined cycle and outputting a reset signal to the CPU when periodicity of the watchdog pulse is disrupted; and
a memory for storing reset information indicating a record thereof when the reset signal is outputted from the monitor circuit, wherein the CPU executes the predetermined fail-safe process based on the reset information stored in the memory after the CPU is once reset and thereafter re-started.
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Accused Products
Abstract
An engine ECU comprises a control CPU for executing engine control and a watchdog circuit for monitoring the CPU. The watchdog circuit stores, whenever a reset signal is outputted to the CPU, a reset information indicating a fault record. The CPU executes, after it is once reset and re-started, the predetermined fail-safe process based on the reset information stored. When a monitor CPU connected to the control CPU for making communication is used as the watchdog circuit, fault detection times X and Y are specified to satisfy the relationship of X≧Y, when the communication fault detection time is defined as X and the watchdog pulse fault detection time as Y.
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Citations
22 Claims
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1. An electronic control unit for a vehicle comprising:
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a CPU having a predetermined fail-safe function required after occurrence of a fault in addition to a vehicle operation control;
a monitor circuit for receiving as an input from the CPU a watchdog pulse generated in a predetermined cycle and outputting a reset signal to the CPU when periodicity of the watchdog pulse is disrupted; and
a memory for storing reset information indicating a record thereof when the reset signal is outputted from the monitor circuit, wherein the CPU executes the predetermined fail-safe process based on the reset information stored in the memory after the CPU is once reset and thereafter re-started. - View Dependent Claims (2, 3, 4, 5)
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6. An electronic control unit for a vehicle comprising:
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a main-CPU for executing a vehicle control;
a monitor circuit for receiving from the main-CPU as an input a watchdog pulse generated in a predetermined cycle, and outputting a reset signal to the main-CPU when periodicity of the watchdog signal is disrupted; and
a sub-CPU connected to the main-CPU for making communication, wherein the main-CPU subsequently resets the sub-CPU when the main-CPU is rest, and wherein the sub-CPU monitors the watchdog pulse outputted to the monitor circuit from the main-CPU and stores a reset record of the main-CPU to a memory until at least a reset signal is outputted from the monitor circuit when the periodicity of the watchdog pulse is disrupted. - View Dependent Claims (7, 8, 9, 10, 11)
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12. An electronic control unit for a vehicle comprising:
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a main-CPU for executing a vehicle control;
a monitor circuit for receiving as an input from the main-CPU a watchdog pulse which is generated in the predetermined cycle, and outputting a reset signal to the main-CPU when the periodicity of the watchdog pulse is disrupted; and
a sub-CPU connected to the main-CPU for making communication, wherein the main-CPU subsequently resets the sub-CPU when the main-CPU is reset, and wherein the sub-CPU monitors the reset signal outputted to the main-CPU from the monitor circuit and stores a reset record in a memory at the time of outputting the reset signal. - View Dependent Claims (13, 14, 15, 16)
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17. An electronic control unit for a vehicle comprising:
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a control CPU for executing a vehicle control; and
a monitor CPU connected to the control CPU for making communication, wherein the monitor CPU includes a first fault detection means which monitors communicating condition with the control CPU, stores a defective condition when a fault occurs in the communicating condition and resets the control CPU, and a second fault detection means which monitors a watchdog pulse outputted from the control CPU, detects a fault from periodicity of the watchdog pulse and stores the condition when a fault occurs in the watchdog pulse, and wherein the fault detection times X, Y are specified to satisfy a relationship of X≧
Y when the fault detection time of the first fault detection means is defined as X and the fault detection time of the second fault detection means as Y. - View Dependent Claims (18, 19)
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20. An electronic control unit comprising:
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a control CPU for executing a vehicle control; and
a monitor CPU connected the control CPU for making communication, wherein the monitor CPU includes a first fault detection means which monitors communicating condition with the control CPU, stores a defective condition when a fault occurs in the communicating condition and resets the control CPU, and a second fault detection means which monitors a watchdog pulse outputted from the control CPU, detects a fault from periodicity of the watchdog pulse and stores the condition when a fault occurs in the watchdog pulse, wherein when a fault detection time of the first fault detection means is defined as X and a fault detection time of the second fault detection means as Y, the fault detection times X and Y are specified to satisfy the relationship of X<
Y, andwherein the monitor CPU determines, when a communication fault is detected by the first fault detection means, whether a reset signal may be outputted to the control CPU and restricts output of the reset signal depending on the result of determination. - View Dependent Claims (21, 22)
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Specification