Method and apparatus for command perception by data value sequencing, allowing a bounded total amount of spurious data

• US 20030061406A1
• Filed: 09/27/2001
• Published: 03/27/2003
• Est. Priority Date: 09/27/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ruehle, Michael Darryl
• Granted Patent: US 6,918,037 B2
• Time in Patent Office: Days
• US Class Current: 710/5
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A system and method for peripheral control. The present invention relates to utilizing device address call sequencing for control of active memory bus peripheral devices, allowing for a bounded amount of spurious data in the sequence.

Claims

1. A system to perceive an event-triggering command, the system comprising:

a first device to perceive said command upon detection of a predetermined sequence of relevant data values within a string of data values, said string of data values including said relevant data values and a number of non-relevant data values, if said string of data values includes ‘

N’

or less non-relevant data values between a first and last relevant data value in said string of data values.

2. The system of claim 1, further comprising a tap line to communicate said plurality of data values between a signal line and said first device.

3. The system of claim 2, wherein the event includes switching between a communication path between the first device and a third device and a communication path between the signal line and the third device.

4. The system of claim 3, wherein the first device is a logic device, the third device is a memory device, and said data values are memory locations.

5. The system of claim 4, wherein the logic device is a Field Programmable Gate Array (FPGA) and the memory device is Synchronous Dynamic Random Access Memory (SDRAM).

6. The system of claim 1, wherein said command is perceived by a data value sequence detector.

7. The system of claim 6, wherein said sequence detector includes a plurality of value sequencing units, each data value sequencing unit including at least one comparator communicatively coupled to at least one counter with N+2 states, each counter having a counter value.

8. The system of claim 7, wherein each value sequencing unit is associated to a distinct relevant data value of the sequence of relevant data values.

9. The system of claim 8, wherein upon recognition of a first relevant data value in the sequence by a first value sequencing unit associated to a first relevant data value, an associated first counter is set to an initial value and receives clocking signals such that

when said first counter expires, then said first counter stops, and

upon recognition of a subsequent first relevant data value, then said first counter is reset and restarted.

10. The system of claim 9, wherein, upon recognition of a second relevant data value by an associated second value sequencing unit while said first counter is not expired, an associated second counter sets its counter value to the counter value of the first counter and then progresses such that

when said second counter expires, then said second counter stops, and

upon recognition of a subsequent second relevant data value while said first counter is not expired, then said second counter sets its counter value to one unit below the counter value of the first counter.

11. The system of claim 10, wherein, upon recognition of a third relevant data value by an associated third value sequencing unit while said second counter is not expired, an associated third counter sets its counter value to the counter value of the second counter and then progresses such that when said third counter expires while said second counter has not expired, then said third counter sets its counter value to one unit below the counter value of the second counter.

12. The system of claim 10, wherein, upon recognition of the last relevant data value in the sequence after sequential recognition of all other relevant data values, if the current counter value of associated last counter is not said terminal value, the event-triggering command is perceived.

13. The system of claim 12, wherein said initial value equals zero, said terminal value equals ‘

N+1’

, and said first counter and second counter progress by incrementation.

14. A method to perceive an event-triggering command, the method comprising:

perceiving, by a first device, said command upon detection of a predetermined sequence of relevant data values within a string of data values, said string of data values including said relevant data values and a number of non-relevant data values, if said string of data values includes ‘

N’

or less non-relevant data values between a first and last relevant data value in said string of data values.

15. The method of claim 14, wherein a tap line is to communicate said plurality of data values between a signal line and said first device.

16. The method of claim 15, wherein the event includes switching between a communication path between the first device and a third device and a communication path between the signal line and the third device.

17. The method of claim 16, wherein the first device is a logic device, the third device is a memory device, and said data values are memory locations.

18. The method of claim 17, wherein the logic device is a Field Programmable Gate Array (FPGA) and the memory device is Synchronous Dynamic Random Access Memory (SDRAM).

19. The method of claim 14, wherein said command is perceived by a data value sequence detector.

20. The method of claim 19, wherein said sequence detector includes a plurality of value sequencing units, each data value sequencing unit including at least one comparator communicatively coupled to at least one counter with N+2 states, each counter having a counter value.

21. The method of claim 20, wherein each value sequencing unit is associated to a distinct relevant data value of the sequence of relevant data values.

22. The method of claim 21, wherein upon recognition of a first relevant data value in the sequence by a first value sequencing unit associated to a first relevant data value, an associated first counter is set to an initial value and receives clocking signals such that

when said first counter expires, then said first counter stops, and

upon recognition of a subsequent first relevant data value, then said first counter is reset and restarted.

23. The method of claim 22, wherein, upon recognition of a second relevant data value by an associated second value sequencing unit while said first counter is not expired, an associated second counter sets its counter value to the counter value of the first counter and then progresses such that

when said second counter expires, then said second counter stops, and

upon recognition of a subsequent second relevant data value while said first counter is not expired, then said second counter sets its counter value to one unit below the counter value of the first counter.

24. The method of claim 23, wherein, upon recognition of a third relevant data value by an associated third value sequencing unit while said second counter is not expired, an associated third counter sets its counter value to the counter value of the second counter and then progresses such that when said third counter expires while said second counter has not expired, then said third counter sets its counter value to one unit below the counter value of the second counter.

25. The method of claim 23, wherein, upon recognition of the last relevant data value in the sequence after sequential recognition of all other relevant data values, if the current counter value of associated last counter is not said terminal value, the event-triggering command is perceived.

26. The method of claim 25, wherein said initial value equals zero, said terminal value equals ‘

N+1’

, and said first counter and second counter progress by incrementation.

27. A system to perceive an event-triggering command, by a logic device, the system comprising:

a signal line to communicate a plurality of memory locations between a host and at least one second device; and

a logic device coupled to said signal line to perceive said command upon detection of a predetermined sequence of relevant memory locations within a string of memory locations on said signal line, said string of memory locations including said relevant memory locations and a number of non-relevant memory locations, if said string of memory locations includes ‘

N’

or less non-relevant memory locations between a first and last relevant memory locations in said string of memory locations.

28. The system of claim 27, further comprising a tap line to communicate said plurality of memory locations between said signal line and said logic device.

29. The system of claim 27, wherein the event includes switching between a communication path between the logic device and a memory device and a communication path between the signal line and the memory device.

30. The system of claim 29, wherein the logic device is a Field Programmable Gate Array (FPGA) and the memory device is Synchronous Dynamic Random Access Memory (SDRAM).