Semiconductor integrated circuit

• US 20030061555A1
• Filed: 09/24/2002
• Published: 03/27/2003
• Est. Priority Date: 09/25/2001
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kamei, Takayuki, Urakawa, Yukihiro
• Application Number:
  US10/252,719
• Publication Number:
  US 20030061555A1
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/3185 Reconfiguring for testing, e.g. LSSD, partitioning

Abstract

A semiconductor integrated circuit includes: a plurality of circuits to be tested, each having the same structure; test paths each provided for one of the circuits to be tested; and a comparator receiving, via the test paths, test outputs sent from the circuits to be tested, comparing the test outputs, and determining whether the test outputs match with each other or not.

Claims

1. A semiconductor integrated circuit comprising:

a plurality of circuits to be tested, each having the same structure;

test paths each provided for one of said circuits to be tested; and

a comparator receiving, via said test paths, test outputs sent from said circuits to be tested, comparing the test outputs, and determining whether the test outputs match with each other or not.

2. The semiconductor integrated circuit according to claim 1, wherein said comparator has a function to select one of said circuits to be tested based on a mode signal, and output a test path output corresponding to the selected circuit to be tested as it is.

3. The semiconductor integrated circuit according to claim 1, wherein said comparator compares the test outputs sent from said circuits to be tested with an expected value, and determines whether the test outputs match with the expected value.

4. The semiconductor integrated circuit according to claim 1, wherein said comparator outputs a test output sent from a predetermined one of said circuits to be tested as it is to a terminal which is different from a terminal used to output a result of the comparison.

5. The semiconductor integrated circuit according to claim 3, further comprising:

a memory circuit storing comparison results of said comparator on whether the test outputs sent from said circuits to be tested match with the expected value or not; and

switching circuits each provided to one of said circuits to be tested, determining whether at least one of said circuits to be tested is defective or not based on an output of said memory circuit, and in the case where there is a defective circuit to be tested, switching the defective circuit to be tested so as to be disabled.

6. The semiconductor integrated circuit according to claim 5, further comprising a redundant circuit having the same structure as said circuits to be tested, wherein said redundant circuit is substituted for the circuit to be tested, which is determined to be defective during the test.

7. The semiconductor integrated circuit according to claim 1, further comprising a disconnecting circuit logically disconnecting the connection between any two of said circuits to be tested during the test.

8. The semiconductor integrated circuit according to claim 2, further comprising a disconnecting circuit logically disconnecting the connection between any two of said circuits to be tested during the test.

9. The semiconductor integrated circuit according to claim 3, further comprising a disconnecting circuit logically disconnecting the connection between any two of said circuits to be tested during the test.

10. The semiconductor integrated circuit according to claim 4, further comprising a disconnecting circuit logically disconnecting the connection between any two of said circuits to be tested during the test.