Highly integrated media access control

• US 20030061623A1
• Filed: 09/26/2002
• Published: 03/27/2003
• Est. Priority Date: 09/27/2001
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Pantelias, Niki Roberta, Denney, Lisa Voigt, Horton, John Daniel Jr., Nazareth, Sean Francis, Moshar, Hooman, Lansing, Shane Patrick
• Granted Patent: US 7,715,437 B2
• Time in Patent Office: Days
• US Class Current: 725/125
• CPC Class Codes: H04L 12/2801 Broadband local area networks
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/52 by attributing bandwidth to queues
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 49/9094 Arrangements for simultaneous transmit and receive, e.g. simultaneous reading/writing from/to the storage element
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers
• CPC Class Codes: H04N 7/17309 Transmission or handling of upstream communications

Abstract

A supervisory communications device, such as a headend device within a cable communications network, monitors and controls communications with a plurality of remote communications devices, such as cable modems, throughout a widely distributed network. The supervisory device allocates bandwidth on the upstream channels by sending MAP messages over its downstream channel. A highly integrated media access controller integrated circuit (MAC IC) operates within the headend to provide lower level DOCSIS processing on signals exchanged with the remote devices. The enhanced functionality of the MAC IC relieves the processing burden on the headend CPU and increases packet throughput. The enhanced functionality includes header suppression and expansion, DES encryption and decryption, fragment reassembly, concatenation, and DMA operations.

Claims

1. A method for processing egress signals within a media access controller integrated circuit (MAC IC), comprising the steps of:

accessing a signal from a physical device coupled to the MAC IC;

pre-processing a header within said signal, said signal being prioritized or stored according to said header;

detecting a fragmented voice and/or data packet from said signal; and

reassembling fragmented frames to produce a reassembled voice and/or data packet in response to said detecting a fragmented voice and/or data packet.

2. The method of claim 1, further comprising the step of:

demodulating and/or FEC-correcting said signal at said physical device prior to said accessing step.

3. The method of claim 1, further comprising the steps of:

extracting a request from said signal; and

forwarding said request to a requests memory.

4. The method of claim 1, further comprising the step of:

deconcatenating said signal.

5. The method of claim 1, further comprising the steps of:

extracting a voice and/or data packet from said signal; and

storing said voice and/or data packet from said extracting step in an upstream memory, wherein said upstream memory includes a plurality of upstream queues.

6. The method of claim 1, further comprising the step of:

terminating said reassembling step in response to detecting an error condition.

7. The method of claim 1, further comprising the step of:

filtering and/or pre-classifying said signal, said filtering and/or pre-classifying being performed prior to said pre-processing step.

8. The method of claim 1, further comprising the step of:

checking said signal for errors.

9. The method of claim 1, further comprising the step of:

checking a key sequence number to decrypt said signal.

10. The method of claim 9, further comprising the step of:

retrieving a BPI key to decrypt said signal.

11. The method of claim 1, further comprising the step of:

detecting a need for additional or fewer unsolicited grants.

12. The method of claim 11, wherein said detecting a need comprises the steps of:

reading a current UGS EHDR from said signal; and

comparing said current UGS EHDR to a prior UGS EHDR to detect said need for additional or fewer unsolicited grants.

13. The method of claim 1, further comprising the step of:

post-processing headers within said reassembled voice and/or data packet.

14. The method of claim 1, further comprising the step of:

deconcatenating said reassembled voice and/or data packet.

15. The method of claim 1, further comprising the step of:

expanding a payload header suppressed packet.

16. The method of claim 15, wherein said expanding step comprises the step of:

querying a PHS memory to retrieve a key to expand said payload header suppressed packet.

17. The method of claim 1, further comprising the step of:

storing said reassembled voice and/or data packet to an upstream memory, wherein said upstream memory includes a plurality of upstream queues.

18. A method for processing ingress signals within a MAC IC, comprising the steps of:

accessing a downstream signal;

producing a DOCSIS header for said downstream signal, said DOCSIS header being added to said downstream signal; and

delivering said downstream signal to a physical device operable to transmit said downstream signal to a remote.

19. The method of claim 18, wherein said producing a DOCSIS header comprises the step of:

producing at least one of a reserved EHDR, a HCS field, and a CRC field.

20. The method of claim 18, wherein said producing a DOCSIS header comprises the step of:

performing payload header suppression.

21. The method of claim 20, wherein said performing payload header suppression comprises the step of:

querying a downstream memory to fetch a PHS rule to perform said payload header suppression.

22. The method of claim 18, further comprising the step of:

encrypting said downstream signal.

23. The method of claim 22, wherein said encrypting comprises the step of:

querying a downstream memory to fetch a DES key to encrypt said downstream signal.

24. The method of claim 18, wherein said accessing a downstream signal comprises the step of:

accessing said downstream signal from a PCI port or a packet port.

25. The method of claim 24, wherein a PCI Ingress receives said downstream signal from said PCI port or a Packet Port Ingress receives said downstream signal from said packet port.

26. The method of claim 18, wherein said accessing a downstream signal comprises the step of:

storing said downstream signal to one of a plurality of downstream priority queues, wherein a PCI descriptor or a DET tag is processed to specify the appropriate priority queue.

27. The method of claim 18, further comprising the step of:

processing said downstream signal to produce a downstream transmission convergence sublayer.

28. The method of claim 18, further comprising the step of:

processing said downstream signal to provide MPEG encapsulation.

29. The method of claim 18, further comprising the step of:

interleaving said downstream signal with a MPEG video frame.

30. The method of claim 18, further comprising the step of:

collecting statistics for DOCSIS OSSI MIB requirements.

31. A single integrated circuit for providing media access control, comprising:

an egress preprocessor for pre-processing an egress signal, wherein said egress preprocessor is configured to receive said egress signal from a physical device coupled to the single integrated circuit; and

a fragment reassembly controller configured to receive a fragmented voice and/or data packet detected from said egress signal, wherein said fragment reassembly controller is operable to reassemble said fragmented voice and/or data packet to produce a reassembled voice and/or data packet.

32. The single integrated circuit of claim 31, wherein said egress preprocessor comprises:

a decrypt or for checking a key sequence number to decrypt said egress signal.

33. The single integrated circuit of claim 31, wherein said egress preprocessor comprises:

a header processor for deconcatenating said egress signal.

34. The single integrated circuit of claim 31, wherein said egress preprocessor comprises:

a header processor for extracting a request from said egress signal.

35. The single integrated circuit of claim 31, further comprising:

an egress postprocessor for post-processing a header within said reassembled voice and/or data packet.

36. The single integrated circuit of claim 35, wherein said egress postprocessor comprises:

a header postprocessor for deconcatenating said reassembled voice and/or data packet.

37. The single integrated circuit of claim 35, wherein said egress postprocessor comprises:

a PHS processor for expanding a payload header suppressed packet.

38. The single integrated circuit of claim 31, further comprising:

an ingress processor for processing an ingress signal.

39. The single integrated circuit of claim 38, wherein said ingress processor comprises:

a header processor for creating a DOCSIS header for said ingress signal.

40. The single integrated circuit of claim 38, wherein said ingress processor comprises:

a PHS processor for suppressing a payload header for said ingress signal.

41. The single integrated circuit of claim 38, further comprising:

an egress postprocessor for post-processing a header within said reassembled voice and/or data packet.

42. The single integrated circuit of claim 41, further comprising:

memory controller means for supporting operations of said egress preprocessor, said fragment reassembly controller, and/or said egress postprocessor.

43. The single integrated circuit of claim 41, further comprising:

memory controller means for supporting operations of said egress postprocessor.

44. The single integrated circuit of claim 41, further comprising:

memory controller means for supporting operations of said ingress processor.

45. The single integrated circuit of claim 41, further comprising:

memory controller means configured to exchange information with a memory coupled to the single integrated circuit, wherein said memory controller means is responsive to support operations of said egress preprocessor, said egress postprocessor and/or said ingress processor.

46. A method for processing egress signals within a media access controller integrated circuit (MAC IC), comprising the steps of:

accessing a signal from a physical device coupled to the MAC IC;

processing a header within said signal, said signal being prioritized or stored according to said header; and

expanding a payload header suppressed packet from said signal in response to detecting a suppressed header within said signal.

47. The method of claim 46, further comprising the step of:

querying a PHS memory to retrieve a key to expand said payload header suppressed packet.

48. The method of claim 46, further comprising the step of:

checking said signal for errors.

49. The method of claim 46, further comprising the step of:

checking a key sequence number to decrypt said signal.

50. The method of claim 49, further comprising the step of:

retrieving a DES key to decrypt said signal.

51. The method of claim 46, further comprising the step of:

deconcatenating said signal.

52. The method of claim 46, further comprising the steps of:

detecting a fragmented voice and/or data packet from said signal; and

reassembling fragmented frames to produce a reassembled voice and/or data packet in response to said detecting a fragmented voice and/or data packet.

53. The method of claim 52, further comprising the step of:

terminating said reassembling step in response to detecting an error condition.

54. The method of claim 52, further comprising the step of:

deconcatenating said reassembled voice and/or data packet.

55. The method of claim 46, further comprising the step of:

demodulating and/or FEC-correcting said signal at said physical device prior to said accessing step.

56. The method of claim 46, further comprising the steps of:

extracting a request from said signal; and

forwarding said request to a requests memory.

57. The method of claim 46, further comprising the steps of:

extracting a voice and/or data packet from said signal; and

storing said voice and/or data packet from said extracting step in an upstream memory, wherein said upstream memory includes a plurality of upstream queues.

58. The method of claim 46, further comprising the step of:

detecting a need for additional or fewer unsolicited grants.

59. The method of claim 58, wherein said detecting a need comprises the steps of:

reading a current UGS EHDR from said signal; and

comparing said current UGS EHDR to a prior UGS EHDR to detect said need for additional or fewer unsolicited grants.

60. A method for processing ingress signals within a MAC IC, comprising the steps of:

accessing a downstream signal;

suppressing a payload header for a packet included in said downstream signal to thereby produce a suppressed header, said suppressed header being added to said downstream signal; and

delivering said downstream signal to a physical device operable to transmit said downstream signal to a remote.

61. The method of claim 60, wherein said suppressing step comprises the step of:

querying a downstream memory to fetch a PHS rule to suppress said payload header.

62. The method of claim 60, further comprising the step of:

producing a DOCSIS header for said downstream signal, said DOCSIS header being added to said downstream signal.

63. The method of claim 62, wherein said producing a DOCSIS header comprises the step of:

producing at least one of a reserved EHDR, a HCS field, and a CRC field.

64. The method of claim 60, further comprising the step of:

encrypting said downstream signal.

65. The method of claim 64, wherein said encrypting comprises the step of:

querying a downstream memory to fetch a DES key to encrypt said downstream signal.

66. The method of claim 60, further comprising the step of:

processing said downstream signal to provide MPEG encapsulation.

67. The method of claim 60, further comprising the step of:

interleaving said downstream signal with a MPEG video frame.

68. The method of claim 60, further comprising the step of:

processing said downstream signal to produce a downstream transmission convergence sublayer.

69. The method of claim 60, further comprising the step of:

collecting statistics for DOCSIS OSSI MIB requirements.

70. The method of claim 60, wherein said accessing a downstream signal comprises the step of:

accessing said downstream signal from a PCI port or a packet port.

71. The method of claim 70, wherein a PCI Ingress receives said downstream signal from said PCI port or a Packet Port Ingress receives said downstream signal from said packet port.

72. The method of claim 60, wherein said accessing a downstream signal comprises the step of:

storing said downstream signal to one of a plurality of downstream priority queues, wherein a PCI descriptor or a DET tag is processed to specify the appropriate priority queue.

73. A single integrated circuit for providing media access control, comprising:

an egress processor for processing an egress signal, wherein said egress processor is configured to receive said egress signal from a physical device coupled to the single integrated circuit; and

a PHS processor for expanding a payload header suppressed packet detected from said egress signal.

74. The single integrated circuit of claim 73, further comprising:

a PHS memory for retrieving a key to expand said payload header suppressed packet in response to queries from said PHS processor.

75. The single integrated circuit of claim 73, wherein said egress processor comprises:

a PHY interface for checking said egress signal for errors.

76. The single integrated circuit of claim 73, wherein said egress processor comprises:

a decrypt or for checking a key sequence number to decrypt said egress signal.

77. The single integrated circuit of claim 73, wherein said egress processor comprises:

a header processor for deconcatenating said egress signal.

78. The single integrated circuit of claim 73, wherein said egress processor comprises:

a fragment reassembly controller configured to receive a fragmented voice and/or data packet detected from said egress signal, wherein said fragment reassembly controller is operable to reassemble said fragmented voice and/or data packet to produce a reassembled voice and/or data packet.

79. The single integrated circuit of claim 73, wherein said egress processor comprises:

a header processor for extracting a request from said egress signal.

80. The single integrated circuit of claim 73, wherein said egress processor comprises:

a detector for detecting a need for fewer or additional unsolicited grants.

81. The single integrated circuit of claim 73, further comprising:

an ingress processor for processing an ingress signal.

82. The single integrated circuit of claim 73, further comprising:

memory controller means for supporting operations of said egress processor, and/or said fragment reassembly controller.

83. The single integrated circuit of claim 82, wherein said ingress processor comprises:

a header processor for creating a DOCSIS header for said ingress signal.

84. The single integrated circuit of claim 82, wherein said ingress processor comprises:

a PHS processor for suppressing a payload header for said ingress signal.

85. The single integrated circuit of claim 82, further comprising:

memory controller means for supporting operations of said ingress processor.

86. A single integrated circuit for providing media access control, comprising:

a header processor for accessing an ingress signal and producing a DOCSIS header for said ingress signal; and

a downstream PHY interface for delivering said ingress signal to a physical device operable to transmit said downstream signal to a remote.

87. The single integrated circuit of claim 86, further comprising:

a PHS processor for suppressing a payload header for said ingress signal.

88. The single integrated circuit of claim 86, further comprising:

memory controller means for supporting operations of said header processor.

89. The single integrated circuit of claim 86, further comprising:

MPEG encapsulator for producing a MPEG frame from said ingress signal.

90. The single integrated circuit of claim 86, further comprising:

encryptor for performing DES encryption on said ingress signal.

91. The single integrated circuit of claim 86, further comprising:

direct memory access for retrieving said ingress signal, and enabling said header processor to access said ingress signal.

92. The single integrated circuit of claim 86, wherein said header processor generates HCS and/or CRC fields to enable error detection for said ingress signal.

93. The single integrated circuit of claim 86, further comprising:

an egress processor for processing an egress signal, wherein said egress processor is configured to receive said egress signal from a physical device coupled to the signal integrated circuit.

94. The single integrated circuit of claim 93, further comprising:

a fragment reassembly controller configured to receive a fragmented voice and/or data packet detected from said egress signal, wherein said fragment reassembly controller is operable to reassemble said fragmented voice and/or data packet to produce a reassembled voice and/or data packet.

95. The single integrated circuit of claim 93, further comprising:

a PHS processor for expanding a payload header suppressed packet in response to detecting a suppressed header in said egress signal.

96. The single integrated circuit of claim 93, further comprising:

a decrypt or for checking a key sequence number to decrypt said egress signal.

97. The single integrated circuit of claim 93, further comprising:

a header processor for deconcatenating said egress signal.

98. The single integrated circuit of claim 93, further comprising:

an upstream PHY interface for checking said signal for errors.

99. The single integrated circuit of claim 86, wherein said physical device is operable to transmit said downstream signal over a wireless medium to said remote.

100. A single integrated circuit for providing media access control, comprising:

a PHS processor for accessing an ingress signal and suppressing a payload header for said ingress signal; and

a downstream PHY interface for delivering said ingress signal to a physical device operable to transmit said downstream signal to a remote.

101. The single integrated circuit of claim 100, further comprising:

a header processor for producing a DOCSIS header for said ingress signal.

102. The single integrated circuit of claim 100, further comprising:

memory controller means for supporting operations of said header processor.

103. The single integrated circuit of claim 100, further comprising:

MPEG encapsulator for producing a MPEG frame from said ingress signal.

104. The single integrated circuit of claim 100, further comprising:

encryptor for performing DES encryption on said ingress signal.

105. The single integrated circuit of claim 100, further comprising:

direct memory access for retrieving said ingress signal, and enabling said header processor to access said ingress signal.

106. The single integrated circuit of claim 100, wherein said header processor generates HCS and/or CRC fields to enable error detection for said ingress signal.

107. The single integrated circuit of claim 100, further comprising:

an egress processor for processing an egress signal, wherein said egress processor is configured to receive said egress signal from a physical device coupled to the signal integrated circuit.

108. The single integrated circuit of claim 107, further comprising:

a fragment reassembly controller configured to receive a fragmented voice and/or data packet detected from said egress signal, wherein said fragment reassembly controller is operable to reassemble said fragmented voice and/or data packet to produce a reassembled voice and/or data packet.

109. The single integrated circuit of claim 107, further comprising:

a PHS processor for expanding a payload header suppressed packet in response to detecting a suppressed header in said egress signal.

110. The single integrated circuit of claim 107, further comprising:

a decrypt or for checking a key sequence number to decrypt said egress signal.

111. The single integrated circuit of claim 107, further comprising:

a header processor for deconcatenating said egress signal.

112. The single integrated circuit of claim 107, further comprising:

an upstream PHY interface for checking said signal for errors.

113. The single integrated circuit of claim 107, wherein said physical device is operable to transmit said downstream signal over a wireless medium to said remote. 114. The single integrated circuit of claim 107, wherein said physical device is operable to transmit said downstream signal via satellite to said remote.