Low-cost lithography

• US 20030061958A1
• Filed: 08/28/2002
• Published: 04/03/2003
• Est. Priority Date: 10/02/2001
• Status: Active Grant

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Granted Patent: US 6,989,603 B2
• Time in Patent Office: Days
• US Class Current: 101/463.1
• CPC Class Codes: G03F 7/0035 Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

The low-cost lithography disclosed in the present invention is based on two approaches: 1. Use a low-precision nF-opening mask to implement high-precision opening-related patterns (e.g. inter-level connections and segmented-lines); 2. Improve the mask re-usability with programmable litho-system and/or logic litho-system. Pattern distribution enables the mask-repair through redundancy. It further enables highly-corrected masks, which provide higher-order correction to clear patterns on wafer.

Claims

1. An inter-level connection, comprising:

a first lower-level line;

an upper-level line;

an inter-level dielectric between said first lower-level line and said upper-level line; and

an opening in said inter-level dielectric, the dimension of said opening along said upper-level line being larger than the width of said first lower-level line;

2. The inter-level connection according to claim 1, wherein the dimension of said opening perpendicular to said upper-level line being equal to the width of said upper-level line.

3. The inter-level connection according to claim 1, further comprising at least one of the following (A)-(D) structures:

(A) a second lower-level line under said opening;

or

(B) an etchstop layer over and/or around both sides of the top surface of said first lower-level line;

or

(C) a tapered sidewall of said opening;

or

(D) a dielectric spacer on at least one sidewall of said opening.

4. A method for forming an opening-related pattern on an integrated circuit, comprising the step of applying an nF-opening mask to a photoresist layer on said integrated circuit, the dimension of the nF-opening pattern formed by said nF-opening mask in said photoresist layer being larger than the width of the line pattern immediately under said nF-opening pattern.

5. An opening-programmable mask, comprising:

an opening-defining plane with at least an opening;

a light-modulating plane with at least a light-modulating cell, said light-modulating cell modulating the exposure light passing through said opening.

6. The opening-programmable mask according to claim 5, wherein said opening-defining plane and said light-modulating plane are located on two separate surfaces.

7. The opening-programmable mask according to claim 5, wherein said light-modulating cell is a light-modulating cell selected from a group including liquid-crystal light-modulating cell, MEMS light-modulating cell, emissive light-modulating cell and three-dimensional light-modulating cell.

8. The opening-programmable mask according to claim 7, wherein said MEMS light-modulating cell further comprises at least one of the following (A)-(C) structures:

(A) an MEMS structure selected from a group including slider, rotor, hinge, roller-shade, digital micro-mirror, and digital light-valve;

or

(B) an electrically floating MEMS structure and/or an electrically shorted MEMS structure;

or

(C) a capacitive driving structure and/or an elastic driving structure and/or a thermal driving structure.

9. The opening-programmable mask according to claim 5, wherein said light-modulating cell comprises a peripheral circuit, said peripheral circuit containing at least a transistor and being dynamic and/or static.

10. A pattern-distributed mask, comprising:

a first mask region;

a second mask region;

the combined range of said first and second mask regions being larger than a full aperture.

11. The pattern-distributed mask according to claim 10, further comprising at least a supporting structure.

12. The pattern-distributed mask according to claim 10, wherein the spacings between all clear features in at least one of said mask regions are larger than 1F.

13. The pattern-distributed mask according to claim 10, wherein said first mask region is a primary mask region, said second mask region is a redundant mask region.

14. A highly-corrected mask, comprising:

a zero-order clear pattern;

an associated higher-order correctional structure;

said zero-order clear pattern and said associated higher-order correctional structure being separated by a spacer film.

15. The highly-corrected mask according to claim 14 being a binary mask.

16. The highly-corrected mask according to claim 14, further comprising:

a first zero-order clear pattern and an associated first higher-order correctional structure;

a second zero-order clear pattern and an associated second higher-order correctional structure;

if the centers of said first and second zero-order clear patterns were located at a distance of 2F, at least a portion of said associated first and second correctional structures would overlap.

17. A lithographic instrument for lowering lithographic cost, comprising:

a stage, said stage providing transporting means for moving an image carrier in a controlled manner;

litho-means for forming a pattern on said stage, said litho-means including programmable litho-means and/or logic litho-means, wherein said programmable litho-means can vary said pattern based on a set of configuration data, said logic litho-means can perform a logic litho-operation based on a plurality of mask patterns.

18. The lithographic instrument according to claim 17, wherein said image carrier is a wafer, or a mask blank, or a master optical disc.

19. The lithographic instrument according to claim 17, further comprising:

an opening-programmable mask; and

means for varying the patterns on said opening-programmable mask between a first and second exposures;

means for changing the relative placement between said opening-programmable mask and said image carrier between said first and second exposures.

20. The lithographic instrument according to claim 17 having an opening-programmable mask, said opening-programmable mask further comprising:

an opening-defining plane;

a light-modulating plane, said light-modulating plane located on a different substrate from said opening-defining plane;

means for changing the relative placement between said opening-defining plane and said light-modulating plane.

21. The lithographic instrument according to claim 17, further comprising:

an opening programmable mask;

image-sensing means for inspecting said opening-programmable mask.

22. The lithographic instrument according to claim 17, further comprising:

a mask or a mask-holder;

means for moving said mask or said mask-holder in a controlled manner.

23. The lithographic instrument according to claim 17, further comprising:

a first projector;

a second projector;

means for merging the mask patterns in said first and second projectors on said image carrier before said image carrier is developed.

24. The lithographic instrument according to claim 17, further comprising:

a first mask-holder;

a second mask-holder;

means for filtering an exposure light by the masks held by said first and second mask-holders before said exposure light reaches said image carrier.

25. The lithographic instrument according to claim 17, further comprising a primary mask and a redundant mask.

26. A litho-programmable integrated circuit (LP-IC) having at least a litho-programmable layer, said litho-programmable layer comprising a plurality of opening-related patterns.

27. The LP-IC according to claim 26, wherein a method for forming said opening-related patterns includes the steps of:

sending an order for said LP-IC with a set of customer data, said order having a volume, said customer data being a source of said opening-related patterns;

receiving a price quote for said order, the overall expected revenue for said order being equal to the product of said volume and said price quote and, being lower than the price of a conventional custom opening-mask set corresponding to said opening-related patterns.

28. The LP-IC according to claim 26 being a litho-programmable application-specific integrated-circuit (LP-ASIC), said LP-ASIC further comprising:

a first conductive layer, all lines in said first conductive layer being aligned along a first direction, said first conductive layer comprising at least a first segmented-line;

a second conductive layer adjacent to and above said first conductive layer, all lines in said second conductive layer being aligned along a second direction, said second conductive layer comprising at least a second segmented-line;

at least an inter-level connection between said first and second conductive layers, said inter-level connection connecting a portion of said first conductive layer to another portion of said second conductive layer.

29. The LP-ASIC according to claim 28, wherein the minimum spacing between the segments in said first or second segmented-lines is equal to the minimum dimension of said inter-level connection along said first direction.

30. The LP-IC according to claim 26, where a method for forming said opening-related patterns includes the steps of sending a set of customer data to the manufacturing site of said LP-IC through a medium, said customer data being a source of said opening-related patterns, said medium including internet, disc, and hard-disk drive,.

31. The LP-IC according to claim 26 being a litho-programmable read-only memory (LP-ROM), said LP-ROM further comprising:

a plurality of read-only memory cells, said read-only memory cells representing data through said opening-related patterns, at least a portion of said data being encrypted;

an on-chip key storage, said key storage storing a key to said encrypted data;

an on-chip decryption engine, said on-chip decryption engine providing means for decrypting the encrypted data based on said key.