Method for making trench MIS device with reduced gate-to-drain capacitance
First Claim
1. A metal-insulator-semiconductor device, comprising:
- a semiconductor substrate including a trench extending into said substrate from a surface of said substrate;
a source region of a first conductivity type adjacent to a sidewall of said trench and to said surface;
a body region of a second conductivity type opposite to said first conductivity type adjacent to said source region and to said sidewall; and
a drain region of said first conductivity type adjacent to said body region and to said sidewall, wherein a stress in said substrate along a bottom portion of said trench does not change appreciably and wherein said trench is lined with a first insulative layer along a portion of said sidewall that abuts said body region and wherein said trench is lined with a second insulative layer along said bottom portion of said trench, said second insulative layer being coupled to said first insulative layer and said second insulative layer being thicker than said first insulative layer.
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Accused Products
Abstract
Trench MIS devices including a thick insulative layer at the bottom of the trench are disclosed, along with methods of fabricating such devices. An exemplary trench MOSFET embodiment includes a thick oxide layer at the bottom of the trench, with no appreciable change in stress in the substrate along the trench bottom. The thick insulative layer separates the trench gate from the drain region at the bottom of the trench yielding a reduced gate-to-drain capacitance making such MOSFETs suitable for high frequency applications. In an exemplary fabrication process embodiment, the thick insulative layer is deposited on the bottom of the trench. A thin insulative gate dielectric is formed on the exposed sidewall and is coupled to the thick insulative layer. A gate is formed in the remaining trench volume. The process is completed with body and source implants, passivation, and metallization.
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Citations
29 Claims
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1. A metal-insulator-semiconductor device, comprising:
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a semiconductor substrate including a trench extending into said substrate from a surface of said substrate;
a source region of a first conductivity type adjacent to a sidewall of said trench and to said surface;
a body region of a second conductivity type opposite to said first conductivity type adjacent to said source region and to said sidewall; and
a drain region of said first conductivity type adjacent to said body region and to said sidewall, wherein a stress in said substrate along a bottom portion of said trench does not change appreciably and wherein said trench is lined with a first insulative layer along a portion of said sidewall that abuts said body region and wherein said trench is lined with a second insulative layer along said bottom portion of said trench, said second insulative layer being coupled to said first insulative layer and said second insulative layer being thicker than said first insulative layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A trench-gate MOSFET, comprising:
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a semiconductor substrate including a trench extending into said substrate from a surface of said substrate;
a source region of a first conductivity type adjacent to a sidewall of said trench and to said surface;
a body region of a second conductivity type opposite to said first conductivity type adjacent to said source region and to said sidewall;
a drain region of said first conductivity type adjacent to said body region and to said sidewall, wherein a stress in said substrate along a bottom portion of said trench does not change appreciably and wherein said trench is lined with a first insulative layer along a portion of said sidewall that abuts said body region and wherein said trench is lined with a second insulative layer along said bottom portion of said trench, said second insulative layer being coupled to said first insulative layer and said second insulative layer being thicker than said first insulative layer; and
a gate region coupled to said first insulative layer and said second insulative layer within said trench. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A trench-gate MOSFET, comprising:
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a semiconductor substrate including a trench extending into said substrate from a surface of said substrate;
a source region of a first conductivity type adjacent to a sidewall of said trench and to said surface;
a body region of a second conductivity type opposite to said first conductivity type adjacent to said source region and to said sidewall;
a drain region of said first conductivity type adjacent to said body region and to said sidewall;
a first insulative layer lining said trench along a portion of said sidewall that abuts said body region;
a second insulative layer lining said trench along a bottom portion of said trench, said second insulative layer being thicker than said first insulative layer and said second insulative layer being coupled to said first insulative layer, wherein a thickness of a transition insulative layer at the juncture of said first insulative layer and said second insulative layer is not less than a thickness of said first insulative layer; and
a gate region coupled to said first insulative layer and said second insulative layer within said trench. - View Dependent Claims (16)
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17. A trench-gate MOSFET, comprising:
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a semiconductor substrate including a trench extending into said substrate from a surface of said substrate;
a source region of a first conductivity type adjacent to a sidewall of said trench and to said surface;
a body region of a second conductivity type opposite to said first conductivity type adjacent to said source region and to said sidewall;
a drain region of said first conductivity type adjacent to said body region and to said sidewall;
a first insulative layer lining said trench along a portion of said sidewall that abuts said body region;
a second insulative layer lining said trench along a bottom portion of said trench, said second insulative layer being thicker than said first insulative layer and said second insulative layer being coupled to said first insulative layer, wherein a first diameter of said trench taken at a vertical midpoint of said second insulative layer is not greater than a second diameter of said trench taken adjacent to said body region; and
a gate region coupled to said first insulative layer and said second insulative layer within said trench. - View Dependent Claims (18)
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19. A method of fabricating an MIS device, comprising:
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providing a semiconductor substrate;
forming a trench in said substrate, said trench including a sidewall and a bottom;
depositing a thick insulative layer on said sidewall and said bottom;
depositing a mask layer in said trench;
etching said mask layer to expose a portion of said thick insulative layer on said sidewall while leaving a portion of said mask layer at said bottom of said trench;
etching said thick insulative layer to form an exposed portion of said sidewall while leaving a portion of said thick insulative layer at said bottom of said trench;
forming a thin insulative layer on said exposed portion of said sidewall; and
forming a gate above said portion of said thick insulative layer and adjacent said thin insulative layer in said trench. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. A method of fabricating an MIS device, comprising:
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providing a semiconductor substrate;
forming a trench in said substrate, said trench including a sidewall and a bottom;
depositing a thick insulative layer on said bottom;
forming a thin insulative layer on said sidewall, said thin insulative layer coupled to said thick insulative layer; and
forming a gate in said trench above said thick insulative layer and adjacent to said thin insulative layer. - View Dependent Claims (27, 28, 29)
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Specification