Method of manufacturing semiconductor device and semiconductor device

• US 20030062575A1
• Filed: 09/27/2002
• Published: 04/03/2003
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tsuchiaki, Masakatsu
• Granted Patent: US 6,815,298 B2
• Time in Patent Office: Days
• US Class Current: 257/382
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518

Abstract

There are provided a semiconductor device that has a SALICIDE structure with low leakage currents, while maintaining shallow source and drain regions. Also a method of manufacturing such a semiconductor device is provided. A method of manufacturing the semiconductor device comprises a step of forming source and drain regions in a first semiconductor layer, the source region and the drain region being separated from each other, a gate insulating film between the source region and the drain region on the first semiconductor layer and a gate electrode on the gate insulating film, a step of forming a metal silicide layer showing a first compound phase on the source region, the drain region and the gate electrode, a step of forming a second semiconductor layer on the metal silicide layer showing the first compound phase where the second semiconductor layer is adapted to react with the metal silicide layer and a step of forming a metal silicide layer showing a second compound phase by causing the second semiconductor layer and the metal silicide layer showing the first compound phase to selectively react with each other.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming source and drain regions in a first semiconductor layer, said source region and said drain region being separated from each other, a gate insulating film between said source region and said drain region on said first semiconductor layer and a gate electrode on said gate insulating film;

forming a metal silicide layer showing a first compound phase on said source region, said drain region and said gate electrode;

forming a second semiconductor layer on said metal silicide layer showing the first compound phase, said second semiconductor layer being adapted to react with said metal silicide layer; and

forming a metal silicide layer showing a second compound phase by causing said second semiconductor layer and said metal silicide layer showing the first compound phase to selectively react with each other.

2. A method according to claim 1, wherein

said metal silicide layer showing the first compound phase is CoSi layer and said metal silicide layer showing the second compound phase is CoSi₂ layer.

3. A method according to claim 1, wherein

said first semiconductor layer is a single crystal silicon layer and said second semiconductor layer is an amorphous silicon layer.

4. A method according to claim 1, wherein

said forming a metal silicide layer showing the second compound phase is conducted by a heat treatment at temperature between 550°

C. and 650°

C.

5. A method according to claim 1, wherein,

after forming the meal silicide layer showing the second compound phase, the unreacted second semiconductor layer is selectively removed from the metal silicide layer showing the second compound phase by isotropic etching.

11. A method according to claim 1, wherein

the concentration of metal atoms in said source region and said drain region is not higher than 1×

10¹⁹ cm<sup>−

3</sup> and the depth of the pn junction formed by said source or drain region and said single crystal silicon layer is not greater than 100 nm.

12. A method according to claim 1, wherein

said metal silicide layer showing the second compound phase is CoSi₂ layer, not less than 17/35 of the film thickness of said metal silicide layer showing the second compound phase being located on said single crystal silicon layer.

13. A method according to claim 1, wherein

said semiconductor device further comprises a silicon layer arranged on said individual metal silicide layer showing the second compound phase and electrically connected to said source region or said drain region.

14. A method according to claim 1, wherein

said semiconductor device further comprises a silicon layer arranged on said individual metal silicide layer and electrically connected to said source region or said drain region.

16. A method according to claim 14, wherein

said second metal silicide layer formed in said first semiconductor layer has a thickness substantially same as a thickness of said second metal silicide layer in said second semiconductor layer.

17. A method according to claim 14, wherein,

before forming said source region and said drain region, extension layers thereof showing the second conductivity type are formed, said extension layers being shallower than said source region and said drain region.

19. A method according to claim 14, wherein

said first metal silicide layer is made of CoSi and said second metal silicide layer is made of CoSi₂.

20. A method according to claim 1, wherein the metal forming said first and second metal silicide layers is at least either Co or Ni or composite metal thereof formed by using Ti.

22. A device according to claim 20, wherein

said metal silicide layer is CoSi₂ layer, not less than 17/35 of the film thickness of said metal silicide layer being located on said single crystal silicon layer.

23. A device according to claim 20, wherein

said semiconductor device further comprises a silicon layer arranged on said metal individual silicide layer and electrically connected to said source region or said drain region.

6. A method of manufacturing a semiconductor device comprising:

forming source and drain regions in a first semiconductor layer, said source region and said drain region being separated from each other, a gate insulating film between said source region and said drain region on said first semiconductor layer and a gate electrode on said gate insulating film;

forming a metal silicide layer showing a first compound phase on said source region, said drain region and said gate electrode;

forming a second semiconductor layer on said metal silicide layer showing the first compound phase, said second semiconductor layer being adapted to react with said metal silicide layer; and

selectively forming a metal silicide layer showing a second compound phase in said second semiconductor layer by causing said second semiconductor layer and said metal silicide layer showing the first compound phase to react with each other in preference to causing said first semiconductor layer and said metal silicide layer showing the first compound phase to react with each other.

7. A method according to claim 6, wherein

said metal silicide layer showing the first compound phase is CoSi layer and said metal silicide layer showing the second compound phase is CoSi₂ layer.

8. A method according to claim 6, wherein

said first semiconductor layer is a single crystal silicon layer and said second semiconductor layer is an amorphous silicon layer.

9. A method according to claim 6, wherein

forming a metal silicide layer showing the second compound phase is conducted by a heat treatment at temperature between 550°

C. and 650°

C.

10. A method according to claim 6, wherein,

after forming the meal silicide layer showing the second compound phase, the unreacted second semiconductor layer is selectively removed from the metal silicide layer showing the second compound phase by isotropic etching.

15. A method of manufacturing a semiconductor device comprising:

forming a gate insulating layer on the surface of a single crystal first semiconductor layer showing a first conductivity type and a semiconductor gate electrode thereon;

forming a source region and a drain region in said first semiconductor layer with said gate electrode sandwiched between them, said source region and said drain region showing the first conductivity type;

forming a first metal silicide layer showing a first compound phase on said source region, said drain region and said gate electrode;

forming an amorphous second semiconductor layer on said first metal silicide layer, said second semiconductor layer being adapted to react with said first metal silicide layer; and

causing said second semiconductor layer and said first metal silicide layer to selectively react with each other, thereby changing at least part of said second semiconductor layer and said first metal silicide layer into a second metal silicide layer showing a second compound phase.

18. A method according to claim 15, wherein

said second metal silicide layer formed in said first semiconductor layer has a thickness smaller than that of said extension layers.

21. A semiconductor device comprising:

source and drain regions formed in a single crystal silicon layer and separated from each other;

a gate insulating film formed between said source region and said drain region on said single crystal silicon layer;

a gate electrode formed on said gate insulating film; and

a metal silicide layer formed on said source region and said drain region;

the concentration of metal atoms in said source region and said drain region being not higher than 1×

10¹⁹ cm<sup>−

3</sup>;

the depth of the pn junction formed by said drain region and said single crystal silicon layer being not greater than 100 nm.