Supercapacitor balancing method and system

• US 20030062876A1
• Filed: 06/17/2002
• Published: 04/03/2003
• Est. Priority Date: 06/18/2001
• Status: Active Grant

• Current Assignee: Saft Finance Sarl (Totalenergies Se)
• Original Assignee: Alcatel SA (Nokia Corporation)
• Inventors: Barrailh, Gerard, Desprez, Philippe, Davat, Bernard, Sharif, Fadi, Rochard, Damien, Rael, Stephane
• Granted Patent: US 6,664,766 B2
• Time in Patent Office: Days
• US Class Current: 320/167
• CPC Class Codes: H02H 7/16 for capacitors for synchronous capacitors H02H7/06
• CPC Class Codes: H02J 7/0016 using shunting, discharge or bypass circuits
• CPC Class Codes: Y02T 10/70 Energy storage systems for electromobility, e.g. batteries

Abstract

The present invention relates to a supercapacitor balancing method including bypassing the current flowing in the supercapacitor from a predetermined threshold voltage at the terminals of the supercapacitor, the bypass current being a function of the voltage at the terminals of the supercapacitor and increasing continuously as a function of the voltage.

The method is characterized in that the bypass current increases between the threshold voltage, for which the bypass current constitutes a minimum bypass current, and a reference voltage, for which the bypass current constitutes a nominal bypass current, and in that the difference between the reference voltage and the threshold voltage is less than 200 mV and the ratio between the nominal bypass current and the minimum bypass current is greater than 100.

Claims

1. A supercapacitor balancing method including bypassing the current flowing in said supercapacitor from a predetermined threshold voltage at the terminals of said supercapacitor, the bypass current being a function of the voltage at the terminals of said supercapacitor and increasing continuously as a function of said voltage, characterized in that said bypass current increases between said threshold voltage, for which said bypass current constitutes a minimum bypass current, and a reference voltage, for which said bypass current constitutes a nominal bypass current, and in that the difference between said reference voltage and said threshold voltage is less than 200 mV and the ratio between said nominal bypass current and said minimum bypass current is greater than 100.

2. A method according to claim 1 wherein said bypass current increases as a linear function of said voltage at the terminals of said supercapacitor.

3. A method according to claim 1 wherein the bypass current is limited as a function of the voltage at the terminals of the supercapacitor.

4. A method according to claim 1 wherein said reference voltage is equal to the end of charging voltage of said supercapacitor.

5. A method according to claim 1 wherein said threshold voltage is equal to the end of charging voltage of said supercapacitor.

6. A method according to claim 1, further including monitoring of the charging current of said supercapacitor as a function of the voltage at the terminals of the supercapacitor by a voltage detector logic function adapted to change from an activated state to a deactivated state if the voltage at the terminals of said supercapacitor exceeds said reference voltage, with the result that the supercapacitor charging current is then reduced, and then to return to the activated state if the voltage at the terminals of said supercapacitor falls below a minimum monitoring voltage.

7. A method according to claim 6, wherein the signal delivered by said voltage detector function is a hysteresis signal.

8. A method according to claim 1, further including monitoring of the charging current of said supercapacitor as a function of the bypass current by a current detector logic function adapted to change from an activated state to a deactivated state if the bypass current is greater than said nominal bypass current, with the result that the charging current of said supercapacitor is then reduced, and then to return to the activated state if the bypass current falls below a minimum monitoring current.

9. A method according to claim 8 wherein the signal delivered by said current detector function is a hysteresis signal.

10. A system for implementing the method according to claim 1, including at least one supercapacitor (11) whose terminals are connected in parallel with a bypass circuit (12) including a current control power amplifier including a MOSFET, a bipolar transistor or an IGBT.

11. A system according to claim 10, wherein a detector unit (14) delivering at least one hysteresis signal representing the voltage at the terminals of said supercapacitor (d_v) and/or the bypass current (d) [sic] is connected to said bypass circuit (12) and supplies said signal (d_v, d_i) to charging means (15) for charging said supercapacitor.

12. A system according to claim 10 including a plurality of supercapacitors (11₁, . . . , 11₅) connected in series and a respective bypass circuit (12₁, . . . , 12₅) connected in parallel with the terminals of each of said supercapacitors (11₁ , . . . , 11₅).

13. A system according to claims 10 and 11, wherein the signals (dv₁, . . . , dv₅, di₁, . . . , di₅) delivered by all of said detector units (12₁, . . . , 12₅) are combined by an AND logic function whose output is sent to said charging means (15).

14. A system according to claim 10 including a plurality of supercapacitors connected in series and a single bypass circuit connected in parallel with the terminals of the set of said supercapacitors.

15. A system according to claim 10, including a plurality of supercapacitors connected in parallel and a single bypass circuit connected in parallel with the terminals of the set of said supercapacitors.