Drive signal generator and image display apparatus

• US 20030063108A1
• Filed: 09/27/2002
• Published: 04/03/2003
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.), Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.), Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Aoki, Tadashi, Isono, Aoji, Sakamoto, Tsutomu, Murayama, Kazuhiko, Shino, Kenji
• Granted Patent: US 6,882,329 B2
• Time in Patent Office: Days
• US Class Current: 345/690
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2081 with combination of amplitude modulation and time modulation space and time error diffusion G09G3/2066
• CPC Class Codes: G09G 3/22 using controlled light sources
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]

Abstract

A drive signal generation circuit which performs gradation control on a load by a drive signal having a stepped waveform. In a case where the wave height value corresponding to input gradation data is Vm (2≦m≦n), the drive signal is caused to rise in such a manner that each output Vk (2≦k≦m) is produced one slot after the output V(k−1) to increase the wave height value V0 (reference potential) to Vm in a stepping manner. One slot corresponds to a unit time of the pulse width modulation. The drive signal is caused to fall in such a manner that each output V(k−1) (1≦k≦m−1) is produced one or two slots after the output Vk to reduce the wave height value from Vm to off level in a stepping manner. A delay circuit is used to delay signals slot by slot. A selection is made from delayed signals according to luminance data to determine a waveform. The circuit is also designed to enable the drive signal waveform rise position to be changed.

Claims

1. A drive signal generation circuit which performs gradation control on a load by a drive signal having a stepped waveform, the drive signal being obtained by performing wave height-value modulation and pulse width modulation in combination using a multistage potential source (V(n−

1)<

Vn) having a potential range from V1 to Vn (n;

an integer equal to or larger than

     2), and in which if the wave height value corresponding to input gradation data is Vm (2≦

m≦

n;

m;

an integer),

the drive signal is caused to rise in such a manner that each output Vk (2≦

k≦

m;

k;

an integer) is produced one slot after the output V(k−

1) to increase the wave height value from off level to Vm in a stepping manner, one slot corresponding to a unit time of the pulse width modulation, and

the drive signal is caused to fall in such a manner that each output V(k−

1) (1≦

k≦

m−

1) is produced one or two slots after the output Vk to reduce the wave height value from Vm to off level in a stepping manner, said drive signal generation circuit comprising;

a start pulse output circuit for generating a pulse with which a start of the output V1 is synchronized;

an end pulse output circuit which outputs a pulse with which an end of the output Vm is synchronized;

a first delay circuit which produces a plurality of delayed outputs by successively delaying one slot at a time the pulse with which the start of the output V1 is synchronized;

a second delay circuit which produces a plurality of delayed outputs by successively delaying in one-slot steps the pulse with which the end of the output Vm is synchronized;

a circuit which generates the pulse with which the start of the output V1 is synchronized, the pulse with which the end of the output Vm is synchronized, and a control signal for setting the pulse width of each output Vk (1≦

k≦

n) from the delayed outputs; and

a pulse width generation circuit which produces a pulse width signal of each output Vk (1≦

k≦

n) by the control signal.

2. A drive signal generation circuit according to claim 1, wherein said signal generation circuit is supplied with a synchronization clock signal for setting the time width of the slot, a start trigger signal for setting the start of the drive signal, and control data formed on the basis of the gradation data, the control data including first data signal for setting the wave height value of the drive signal, and a second data signal for setting the pulse width of the wave height value, and a third data signal for setting the stepped shape of a falling portion of the drive signal;

at least said start pulse output circuit, said end pulse output circuit, and said first and second delay circuits are controlled by the synchronization clock signal;

said start pulse output circuit is controlled by the start trigger signal;

said end pulse output circuit is controlled by the start trigger signal and the second data signal; and

said circuit which produces the control signal is controlled by the third data signal and the first data signal.

3. A drive signal generation circuit according to claim 2, wherein said start pulse output circuit produces the start pulse in synchronization with the synchronization clock signal on the basis of the start trigger signal;

said end pulse output circuit has a counter which is reset by the start trigger signal, and which counts the synchronization clock signal, and a comparator which generates the end pulse when a count value of said counter and the second data signal coincide with each other;

said first delay circuit produces (n−

1) number of delayed outputs by delaying the start pulse by (j−

1) slots with respect to each j in 2≦

j≦

n (j;

integer);

said second delay circuit produces n number of delayed outputs by delaying the end pulse by j slots with respect to each j in 1≦

j≦

n;

said circuit which outputs the control signal selects the start pulse or one of the plurality of delayed outputs obtained by delaying the start pulse, and the end pulse or one of the plurality of delayed outputs obtained by delaying the end pulse, on the basis of the first and third data signals with respect to each output Vk, and outputs the selected pulses as an output start pulse and an output end pulse of the output Vk; and

said pulse width generation circuit outputs, as the pulse width signal of each output Vk, a signal which is turned on by being timed to the output start pulse of the output Vk and is turned off by being timed to the output end pulse of the output Vk.

4. A drive signal generation circuit according to claim 1, wherein a plurality of said signal generation circuits are used by being combined in parallel with each other to respectively perform gradation control on loads connected in parallel with each other;

said start pulse output circuit selects one of a first timing in the first half of the pulse width control period, and a third timing preceding a second timing in the second half of the pulse width control period by at least a period of time corresponding to the pulse width of the output Vm to generate a pulse with which the start of the output V1 is synchronized; and

said end pulse output circuit selects one of a fourth timing coming after the first timing with at least a period of time corresponding to the pulse width of the output Vm, and the second timing to generate a pulse with which the end of the output Vm is synchronized.

5. A drive signal generation circuit according to claim 4, wherein said signal generation circuit is supplied with a synchronization clock signal for setting the time width of the slot, a start trigger signal for setting the start of the drive signal, and control data formed on the basis of the gradation data, the control data including first data signal for setting the wave height value of the drive signal, and second data signal for setting the pulse width of the wave height value, and third data signal for setting the stepped shape of a falling portion of the drive signal, and a rise sync/fall sync change signal;

said drive signal generation circuit further comprises a counter which is reset by the start trigger signal, and which counts the synchronization clock signal;

at least said start pulse output circuit, said end pulse output circuit, and said first and second delay circuits are controlled by the synchronization clock signal;

said start pulse output circuit is controlled by the start trigger signal, an output from said counter, and the rise sync/fall sync change signal;

said end pulse output circuit is controlled by the start trigger signal, the second data signal, the output from said counter, and the rise sync/fall sync change signal;

said circuit which produces the control signal is controlled by the third data signal and the first data signal; and

the second data signal for fall synchronization is set as the difference between data for setting the limit position of the trailing end of the output Vm and the second data signal for rise synchronization.

6. A drive signal generation circuit according to claim 5, wherein said start pulse output circuit includes a circuit which generates a first pulse in synchronization with the synchronization clock signal on the basis of the start trigger signal, a comparator which generates a second pulse when the count value of said counter and the second data signal coincide with each other, and a first selecting circuit which selects one of the first and second pulses on the basis of the rise sync/fall sync change signal and outputs the selected pulse as a start pulse;

said end pulse output circuit has a second selecting circuit which selects one of the second data and the limit position setting data on the basis of the rise sync/fall sync change signal, and a comparator which generates the end pulse when data output from said second selecting circuit and the count value of said counter coincide with each other;

said first delay circuit produces (n−

1) number of delayed outputs by delaying the start pulse by (j−

1) slots with respect to each j in 2≦

j≦

n (j;

integer);

said second delay circuit produces n number of delayed outputs by delaying the end pulse by j slots with respect to each j in 1≦

j≦

n;

said circuit which outputs the control signal selects the start pulse or one of the plurality of delayed outputs obtained by delaying the start pulse, and the end pulse or one of the plurality of delayed outputs obtained by delaying the end pulse, on the basis of the first and third data with respect to each output Vk, and outputs the selected pulses as an output start pulse and an output end pulse of the output Vk; and

said pulse width generation circuit outputs, as the pulse width signal of each output Vk, a signal which is turned on by being timed to the output start pulse of each output Vk and is turned off by being timed to each output end pulse of the output Vk.

7. A drive signal generation circuit according to claim 1 or 4, further comprising an output circuit which produces an output of each wave height value, and which produces only the output having the maximum wave height value when on signals are simultaneously generated with respect to two or more outputs Vk.

8. A drive signal generation circuit according to claim 1 or 4, wherein the load is a light-emitting device.

9. A drive signal generation circuit which generates a drive signal for gradation control on a light-emitting device, the drive signal having a waveform formed by selecting a signal level from a plurality of n wave height values corresponding to different light-emitting states, said drive signal generation circuit comprising:

a circuit A which outputs a raise signal with which a rise in the waveform of the drive signal is synchronized;

a circuit B which outputs at least (n−

1) number of delayed signals with an incremental delay of a predetermined time period from the raise signal; and

a circuit C which outputs the drive signal having a rising shape formed in the waveform of the drive signal in such a manner that the signal level is raised in synchronization with the raise signal from a signal level corresponding to an off state of the light-emitting device to the lowest of the n wave height values, and is thereafter increased to the higher wave height value one step at a time in synchronization with the delayed signals with the delay of the predetermined time period until a predetermined wave height value determined by input gradation data is reached.

10. A drive signal generation circuit according to claim 9, further comprising:

a circuit D that outputs a fall-causing signal with which a fall of the drive signal waveform from the predetermined wave height value is synchronized; and

a circuit E which outputs at least n number of delayed fall signals with an incremental delay of a predetermined time period from the fall-causing signal,

wherein the circuit C causes the signal level to fall to the wave height value one step lower than the predetermined wave height value in synchronization with the fall-causing signal, and thereafter causes the signal level to fall to the lower wave height values one step at a time in synchronization with the delayed fall-causing signals selected according to the input gradation data.

11. A drive signal generation circuit according to claim 9, wherein said circuit A outputs the raise signal by a timing based on a trigger signal and raise position data externally supplied.

12. A drive signal generation circuit according to claim 10, wherein said circuit A outputs the raise signal by a timing based on a trigger signal and raise position data externally supplied.

13. A drive signal generation circuit according to claim 11, further comprising:

a circuit D which outputs a fall-causing signal according to a timing based on the trigger signal and fall position data externally supplied along with the trigger signal, a fall of the drive signal waveform from the predetermined wave height value being synchronized with the fall-causing signal; and

a circuit E which outputs at least n number of delayed fall-causing signals with an incremental delay of a predetermined time period from the fall-causing signal,

wherein the circuit C causes the signal level to fall to the wave height value one step lower than the predetermined wave height value in synchronization with the fall-causing signal, and thereafter causes the signal level to fall to the lower wave height values one step at a time in synchronization with the delayed fall-causing signals selected according to the input gradation data.

16. A drive signal generation circuit according to any one of claims 10, wherein the predetermined wave height value is the mth wave height value from the lowest of the n number of wave height values (m≦

n), and the selection of the delayed fall-causing signals is made from the (m−

1) number among the n number of delayed fall-causing signals.

18. An image display apparatus comprising a plurality of light-emitting devices and a drive signal generation circuit according to any one of claims 9, the drive signal generation circuit generating drive signals for driving the plurality of light-emitting devices.

19. An image display apparatus according to claim 18, wherein said plurality of light-emitting devices are connected in a matrix configuration by a plurality of scanning wirings and a plurality of modulation wirings, and a plurality of said drive signal generation circuits are respectively connected to the modulation wirings.

20. An image display apparatus according to claim 19, further comprising a scanning circuit, wherein said scanning circuit selects said plurality of scanning wirings one after another and applies a selecting potential to the selected scanning wiring, and wherein said plurality of drive signal generation circuits supplies the drive signals for driving to the plurality of light-emitting devices connected to each of the plurality of scanning wirings in a time period during which the scanning wiring is selected.

14. A drive signal generation circuit which generates a drive signal for gradation control on a light-emitting device, the drive signal having a wave form formed by selecting a signal level from a plurality of n wave height values corresponding to different light-emitting states, said drive signal generation circuit comprising:

a circuit D which outputs a fall-causing signal with which a fall in signal level from a predetermined wave height value to a wave height value one step lower is synchronized;

a circuit E which outputs at least n number of delayed fall-causing signals with an incremental delay of a predetermined time period from the fall-causing signal; and

a circuit C which causes the signal level to fall to the wave height value one step lower than the predetermined wave height value in synchronization with the fall-causing signal, and thereafter causes the signal level to fall to the lower wave height values one step at a time in synchronization with the delayed fall-causing signals selected according to the input gradation data.

15. A drive signal generation circuit according to claim 14, wherein said circuit D outputs the fall-causing signal by a timing based on a trigger signal and fall-causing position data externally supplied.

17. A drive signal generation circuit according to any one of claims 14, wherein the predetermined wave height value is the mth wave height value from the lowest of the n number of wave height values (m≦

n), and the selection of the delayed fall-causing signals is made from the (m−

1) number among the n number of delayed fall-causing signals.

21. An image display apparatus comprising:

a plurality of scanning wirings and a plurality of modulation wirings connected in a matrix configuration;

light-emitting devices provided in correspondence with points of intersection of said scanning wirings and said modulation wirings; and

a drive signal generation circuit which generates a drive signal for performing gradation control on each of said light-emitting devices according in an input luminance signal,

wherein the drive signal is obtained by modulation which is a combination of wave height-value modulation and pulse width modulation, and has a waveform in which the wave height value is successively increased in a stepping manner from a rise start point determined by a gradation value in a luminance signal related to the drive signal, and is successively reduced in a stepping manner from a fall start point determined irrespective of the gradation value.

22. An image display apparatus comprising:

a plurality of scanning wirings and a plurality of modulation wirings connected in a matrix configuration;

light-emitting devices provided in correspondence with points of intersection of said scanning wirings and said modulation wirings; and

a drive signal generation circuit which generates a drive signal for performing gradation control on each of said light-emitting devices according to an input luminance signal,

wherein the drive signal is obtained by modulation which is a combination of wave height-value modulation and pulse width modulation, and wherein, in a time period during which one of said plurality of scanning wirings is selected, each of part of the plurality of drive signals for gradation control on the plurality of light-emitting devices connected to the selected one of the scanning wirings has a waveform in which the wave height value is successively increased in a stepping manner from a rise start point determined by a gradation value in a luminance signal related to the drive signal, and is successively reduced in a stepping manner from a fall start point determined irrespective of the gradation value, and each of the other drive signals has a waveform in which the wave height value is successively reduced from a fall start point determined by a gradation value in a luminance signal related to the drive signal, and is, before the start of falling, successively increased in a stepping manner from a rise start point determined irrespective of the gradation value.

23. A control method of controlling a light-emitting device by a drive signal which is wave height-value controlled with respect to a plurality of discrete wave height values, and which is pulse width controlled with respect to discrete pulse widths, said method comprising:

forming a digital video word including a plurality of subwords from gradation data;

selecting a part of a plurality of signals each having a predetermined difference in time from a predetermined timing on the basis of a part of, not the whole of, the plurality of subwords to produce a plurality of pulse width control signals in each of which a predetermined active time is specified; and

controlling the pulse width of each wave height value of the drive signal according to the active time.

24. A control method according to claim 23, wherein the drive signal is controlled so that each of a rising portion and a falling portion of the waveform of the drive signal is stepped.

25. A control method according to claim 23, wherein the digital video word includes a wave height value subword indicating wave height values to be used in the plurality of wave height values, and a pulse width subword indicating the pulse width of the waveform.

26. A control method according to claim 25, wherein the digital video word includes a subword indicating the shape of an end portion of the waveform of the drive signal.