Directional audio signal processing using an oversampled filterbank

• US 20030063759A1
• Filed: 08/07/2002
• Published: 04/03/2003
• Est. Priority Date: 08/08/2001
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: AMI Semiconductor Inc (ON Semiconductor Corporation)
• Inventors: Nadjar, Hamid Sheikhzadeh, Brennan, Robert L., Schneider, Todd, Chau, Edward
• Granted Patent: US 7,359,520 B2
• Time in Patent Office: Days
• US Class Current: 381/92
• CPC Class Codes: H04R 25/405 by combining a plurality of transducers
• CPC Class Codes: H04R 25/407 Circuits for combining signals of a plurality of transducers
• CPC Class Codes: H04R 25/507 implemented by neural network or fuzzy logic
• CPC Class Codes: H04R 3/005 for combining the signals of two or more microphones specially adapted for hearing aids H04R25/407

Abstract

A directional signal processing system for beamforming information signals. The system includes an oversampled filterbank, which has an analysis filterbank for transforming the information signals in time domain into channel signals in transform domain, a synthesis filterbank and a signal processor. The signal processor processes the outputs of the analysis filterbank for beamforming the information signals. The synthesis filterbank transforms the outputs of the signal processor to a single information signal in time domain.

Claims

1. A directional signal processing system for beamforming a plurality of information signals, said directional signal processing system comprising:

a plurality of microphones;

an oversampled filterbank comprising at least one analysis filterbank for transforming a plurality of information signals in time domain from the microphones into a plurality of channel signals in transform domain, and one synthesis filterbank and

a signal processor for processing the outputs of said analysis filterbank for beamforming said information signals,

the synthesis filterbank transforming the outputs of said signal processor to a single information signal in time domain.

2. A directional processing system as claimed in claim 1, wherein said transform domain is a frequency domain.

3. The directional processing system as claimed in claim 1 further comprises at least one of any of the following:

a post-filter provided between said signal processor and said synthesis filterbank;

a controller for controlling said post-filter;

a voice activity detector;

a target-to-jammer ratio estimator;

a signal-to-noise ratio estimator;

an analog-to-digital convertor for converting said information signals to a plurality of digital information signals for supplying said digital information signals to said analysis filterbank;

a digital-to-analog convertor receiving the outputs of said synthesis filterbank for converting a digital information signal to analog information signal;

a combination matrix provided between said analog-to-digital convertor and said analysis filterbank for pre-processing of said information signals in time domain;

an active noise processor comprising a microphone and a loop filter.

4. The directional processing system as claimed in claim 2 further comprises at least one of any of the following:

a post-filter provided between said signal processor and said synthesis filterbank;

a controller for controlling said post-filter;

a voice activity detector;

a target-to-jammer ratio estimator;

a signal-to-noise ratio estimator;

an analog-to-digital convertor for converting said information signals to a plurality of digital information signals for supplying said digital information signals to said analysis filterbank;

a digital-to-analog convertor receiving the outputs of said synthesis filterbank for converting a digital information signal to analog information signal;

a combination matrix provided between said analog-to-digital convertor and said analysis filterbank for pre-processing of said information signals in time domain;

an active noise processor comprising a microphone and a loop filter.

5. The directional processing system as claimed in claim 1, wherein the analysis filterbank applies at least one fractional delay impulse response to at least one filterbank prototype window.

6. A directional processing system as claimed in claim 3, wherein said controller controls said post-filter based on the outputs of at least one of any of the following:

said voice activity detector;

said target-to-jammer ratio estimator;

said signal-to-noise ratio estimator.

7. A directional processing system as claimed in claim 4, wherein said controller controls said post-filter based on the outputs of at least one of any of the following:

said voice activity detector;

said target-to-jammer ratio estimator;

said signal-to-noise ratio estimator.

8. A directional processing system as claimed in claim 3, wherein said combination matrix is a FIR filter.

9. A directional processing system as claimed in claim 4, wherein said combination matrix is a FIR filter.

10. A directional processing system as claimed in claim 3, wherein said combination matrix is an IIR filter.

11. A directional processing system as claimed in claim 4, wherein said combination matrix is an IIR filter.

12. A directional processing system as claimed in claim 1, wherein said signal processor comprises:

at least one multiplier for multiplying the outputs of said analysis filterbank with at least one weight factor; and

at least one summation circuit for summing the outputs of said multiplier to form the channel signals.

13. A directional processing system as claimed in claim 3, wherein said signal processor further comprises:

at least one multiplier for multiplying the outputs of said analysis filterbank with at least one weight factor; and

at least one summation circuit for summing the outputs of said multiplier to form the channel signals.

14. A directional processing system as claimed in claim 4, wherein said signal processor further comprises:

at least one multiplier for multiplying the outputs of said analysis filterbank with at least one weight factor; and

at least one summation circuit for summing the outputs of said multiplier to form the channel signals.

15. A directional processing system as claimed in claim 12, wherein said signal processor further comprises an adaptive processor for adjusting said weight factor.

16. A directional processing system as claimed in claim 13, wherein said signal processor further comprises an adaptive processor for adjusting said weight factor.

17. A directional processing system as claimed in claim 14, wherein said signal processor further comprises an adaptive processor for adjusting said weight factor.

18. A directional processing system as claimed in claim 15, wherein said adaptive processor adjusts said weight factor based on the outputs of at least one of any of the following:

a voice activity detector;

a target-to-jammer ratio estimator;

a signal-to-noise ratio estimator;

19. A directional processing system as claimed in claim 16, wherein said adaptive processor adjusts said weight factor based on the outputs of at least one of any of the following:

a voice activity detector;

a target-to-jammer ratio estimator;

a signal-to-noise ratio estimator;

20. A directional processing system as claimed in claim 17, wherein said adaptive processor adjusts said weight factor based on the outputs of at least one of any of the following:

a voice activity detector;

a target-to-jammer ratio estimator;

a signal-to-noise ratio estimator;

21. A directional processing system as claimed in claim 1, wherein said signal processor comprises:

at least one fixed beamformer receiving the outputs of said analysis filterbank for beamforming said information signals with a specific beampattern; and

at least one multiplier for multiplying the outputs of said fixed beamformer with at least one weight factor.

22. A directional processing system as claimed in claim 3, wherein said signal processor further comprises:

at least one fixed beamformer receiving the outputs of said analysis filterbank for beamforming said information signals with a specific beampattern; and

at least one multiplier for multiplying the outputs of said fixed beamformer with at least one weight factor.

23. A directional processing system as claimed in claim 4, wherein said signal processor further comprises:

at least one fixed beamformer receiving the outputs of said analysis filterbank for beamforming said information signals with a specific beampattern; and

at least one multiplier for multiplying the outputs of said fixed beamformer with at least one weight factor.

24. A directional processing system as claimed in claim 21, wherein said signal processor farther comprises at least one of any of the following:

a summation circuit for summing the outputs of said multiplier to form the channel signals;

an adaptive processor for adjusting said weight factor.

25. A directional processing system as claimed in claim 22, wherein said signal processor further comprises at least one of any of the following:

a summation circuit for summing the outputs of said multiplier to form the channel signals;

an adaptive processor for adjusting said weight factor.

26. A directional processing system as claimed in claim 23, wherein said signal processor further comprises at least one of any of the following:

a summation circuit for summing the outputs of said multiplier to form the channel signals;

an adaptive processor for adjusting said weight factor.

27. A directional processing system as claimed in claim 21, wherein at least one fixed beamformer comprises a circuit for processing the channel signals for achieving approximately linear phase response within the channel, the circuit applies one or more filter to at least one channel signal.

28. A directional processing system as claimed in claim 22, wherein at least one fixed beamformer comprises a circuit for processing the channel signals for achieving approximately linear phase response within the channel, the circuit applies one or more filter to at least one channel signal.

29. A directional processing system as claimed in claim 23, wherein at least one fixed beamformer comprises a circuit for processing the channel signals for achieving approximately linear phase response within the channel, the circuit applies one or more filter to at least one channel signal.

30. A directional processing system as claimed in claim 27, wherein the filter is an IIR filter.

31. A directional processing system as claimed in claim 28, wherein the filter is an IIR filter.

32. A directional processing system as claimed in claim 29, wherein the filter is an IIR filter.

33. A directional processing system as claimed in claim 1, wherein said signal processor comprises:

at least one multiplier for multiplying the outputs of said analysis filterbank with at least one beamforming filter tap; and

at least one summation circuit for summing the outputs of said multiplier to form the channel signals for beaforming said information signals.

34. A directional processing system as claimed in claim 3, wherein said signal processor further comprises:

at least one multiplier for multiplying the outputs of said analysis filterbank with at least one beamforming filter tap; and

at least one summation circuit for summing the outputs of said multiplier to form the channel signals for beaforming said information signals.

35. A directional processing system as claimed in claim 4, wherein said signal processor further comprises:

at least one multiplier for multiplying the outputs of said analysis filterbank with at least one beamforming filter tap; and

at least one summation circuit for summing the outputs of said multiplier to form the channel signals for beaforming said information signals.

36. A directional processing system as claimed in claim 33, wherein said signal processor further comprises at least one of any of the following:

an adaptive processor for adjusting said beamforming filter tap;

a circuit for processing a plurality of channel signals to achieve approximately linear phase response within the channel, the circuit applying one or more filter to at least one channel signal;

a processor for dividing the outputs of said analysis filterbank such that at least one channel signal can be processed differently from the other channel signals.

37. A directional processing system as claimed in claim 34, wherein said signal processor further comprises at least one of any of the following:

an adaptive processor for adjusting said beamforming filter tap;

a circuit for processing a plurality of channel signals to achieve approximately linear phase response within the channel, the circuit applying one or more filter to at least one channel signal;

a processor for dividing the outputs of said analysis filterbank such that at least one channel signal can be processed differently from the other channel signals.

38. A directional processing system as claimed in claim 35, wherein said signal processor further comprises at least one of any of the following:

an adaptive processor for adjusting said beamforming filter tap;

a circuit for processing a plurality of channel signals to achieve approximately linear phase response within the channel, the circuit applying one or more filter to at least one channel signal;

a processor for dividing the outputs of said analysis filterbank such that at least one channel signal can be processed differently from the other channel signals.

39. A directional processing system as claimed in claim 36, wherein said circuit is an IIR filter.

40. A directional processing system as claimed in claim 37, wherein said circuit is an IIR filter.

41. A directional processing system as claimed in claim 38, wherein said circuit is an IIR filter.

42. A directional processing system as claimed in claim 36, wherein said processor for dividing the outputs of said analysis filterbank includes at least one high-pass filter and at least one low-pass filter.

43. A directional processing system as claimed in claim 37, wherein said processor for dividing the outputs of said analysis filterbank includes at least one high-pass filter and at least one low-pass filter.

44. A directional processing system as claimed in claim 38, wherein said processor for dividing the outputs of said analysis filterbank includes at least one high-pass filter and at least one low-pass filter.

45. A directional processing system as claimed in claim 36, wherein said summation circuit receives the outputs of said multiplier and at least one of any of the channel signals that have been processed differently.

46. A directional processing system as claimed in claim 37, wherein said summation circuit receives the outputs of said multiplier and at least one of any of the channel signals that have been processed differently.

47. A directional processing system as claimed in claim 38, wherein said summation circuit receives the outputs of said multiplier and at least one of any of the channel signals that have been processed differently.

48. A directional processing system as claimed in claim 1, wherein said signal processor comprises at least one of any of the following:

a neural network receiving the outputs of said analysis filterbank;

a multiplier for multiplying the outputs of said neural network with the outputs of said analysis filterbank;

a summation circuit for summing the outputs of said multiplier to form a plurality of channel signals;

a post-filter provided between said summation circuit and said synthesis filterbank;

a controller for controlling said post-filter.

49. A directional processing system as claimed in claim 2, wherein said signal processor comprises at least one of any of the following:

a neural network receiving the outputs of said analysis filterbank;

a multiplier for multiplying the outputs of said neural network with the outputs of said analysis filterbank;

a summation circuit for summing the outputs of said multiplier to form a plurality of channel signals;

a post-filter provided between said summation circuit and said synthesis filterbank;

a controller for controlling said post-filter.

50. A directional processing system as claimed in claim 48, wherein said neural network is a Cascaded Hybrid Neural Network.

51. A directional processing system as claimed in claim 49, wherein said neural network is a Cascaded Hybrid Neural Network.

52. A method of processing a plurality of channel signals for achieving approximately linear phase response within the channel, said method comprising the step of performing filtering by applying one or more filter to at least one channel signal.

53. A method of processing a plurality of channel signals as claimed in claim 52, wherein said filter is an IIR filter.

54. A method of processing at least one information signal in time domain for achieving approximately linear phase response, said method comprising the step of performing an oversampled transformation using at least one oversampled analysis filterbank, said oversampled analysis filterbank applying at lease one fractional delay impulse response to at least one filterbank prototype window.