Method and apparatus for distortionless peak reduction

• US 20030064737A1
• Filed: 09/28/2001
• Published: 04/03/2003
• Est. Priority Date: 09/28/2001
• Status: Abandoned Application

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Carebo, Stellan, Ghafouri, Ari, Hyllander, Thord, Eriksson, Patrik, Petersson, Peter Magnus
• Application Number:
  US09/964,865
• Publication Number:
  US 20030064737A1
• Time in Patent Office: Days
• US Class Current: 455/501
• CPC Class Codes: H04L 27/2614 Peak power aspects
• CPC Class Codes: H04L 27/2624 by soft clipping

Abstract

The present invention reduces the peak-to-average power ratio (PAR) of a signal while at the same time providing improved signal-to-noise-and-distortion and increased dynamic range. In the context of a transmitter, the PAR of an input signal is reduced so that one or more elements of a transmitter can be operated with increased dynamic range. However, the initial PAR is restored before the signal is transmitted thereby removing distortion generated as the result of the PAR reduction. The initial PAR is reduced in the digital domain, converted into the analog domain, and then restored in the analog domain.

Claims

1. A method for reducing a peak-to-average ratio (PAR) of a signal, comprising:

(a) receiving a input signal;

(b) generating an offsetting signal associated with the input signal;

(c) combining the input signal and the offsetting signal so that the offsetting signal reduces the PAR of the input signal to produce a combined signal;

(d) processing the combined signal and the offsetting signal; and

(e) combining the processed combined signal and the processed offsetting signal.

2. The method in claim 1, wherein the input signal is a multi-carrier signal.

3. The method in claim 1, wherein the offsetting signal is an anti-phase signal.

4. The method in claim 1, wherein the processing includes converting the combined signal and the offsetting signal from digital form into analog form and the analog combined signal and the analog offsetting signal are combined in step (e) to generate an analog combined signal.

5. The method in claim 4, further comprising:

transmitting the analog combined signal.

6. The method in claim 5, further comprising:

performing analog processing on the analog combined signal before transmission.

7. The method in claim 5, wherein the processing includes analog processing the combined signal and the offsetting signal before the combining and transmission.

8. The method in claim 4, wherein the offsetting signal is converted into analog form using plural digital-to-analog converters.

9. The method in claim 4, wherein the combined signal and the offsetting signal are each converted into analog form using a respective digital-to-analog converter, and wherein each digital-to-analog converter has substantially the same characteristics.

10. The method in claim 4, wherein the combined signal and the offsetting signal are each converted into analog form using a respective digital-to-analog converter, and wherein each digital-to-analog converter has different characteristics.

11. A method of reducing a peak-to-average ratio (PAR) of a signal, comprising:

receiving a digital input signal;

formulating an anti-phase signal for the input signal;

combining the input and anti-phase signals to produce a peak-limited digital signal;

converting the peak-limited digital signal in a first digital-to-analog converter into a peak-limited analog signal;

converting the anti-phase digital signal in a second digital-to-analog converter into an anti-phase analog signal; and

combining the peak-limited and anti-phase analog signals to produce a combined analog signal.

12. The method in claim 11, further comprising:

changing a sign of the anti-phase signal or inverting the anti-phase signal before combining the peak-limited and anti-phase analog signals.

13. The method in claim 11, wherein the anti-phase signal limits the input signal peak to a threshold associated with a range of the first digital-to-analog converter.

14. The method in claim 13, wherein threshold corresponds to a full scale range of the first digital-to-analog converter such that the peak-limited analog signal does not contribute substantial quantization noise from the conversion in the first digital-to-analog converter to the combined analog signal.

15. The method in claim 14, wherein a dynamic range associated with the digital-to-analog conversion of the input signal using the first and second digital-to-analog converter is greater than using only a single digital-to-analog converter.

16. The method in claim 11, wherein the combining removes distortion caused by peak-limiting the input signal.

17. The method in claim 11, further comprising:

transmitting the combined analog signal.

18. The method in claim 17, further comprising:

performing analog processing on the combined analog signal before transmission.

19. The method in claim 17, further comprising:

analog processing the peak-limited analog signal and the anti-phase analog signal before the combining and transmission.

20. The method in claim 11, wherein the first and second digital-to-analog converters have substantially the same characteristics.

21. The method in claim 11, wherein the first and second digital-to-analog converters have different characteristics.

22. A method, comprising:

reducing in a digital domain a peak-to-average ratio (AR) of a signal having an initial PAR;

converting the reduced PAR digital signal into the analog domain to provide a reduced PAR analog signal; and

removing distortion in the reduced PAR analog signal caused by the PAR reducing step in the analog domain.

23. The method in claim 22, wherein the removing step includes restoring the initial PAR from the reduced PAR analog signal.

24. The method in claim 22, wherein the PAR reducing step is accomplished using an anti-phase signal to offset peaks of the signal in the digital domain.

25. The method in claim 24, further comprising:

transforming the anti-phase signal into an in-phase signal;

converting the in-phase signal into the analog domain; and

wherein the restoring step includes combining the analog in-phase signal with the reduced PAR analog signal.

26. Apparatus for reducing a peak-to-average ratio (PAR) of an input signal, comprising:

first electronic circuitry configured to generate an offsetting signal associated with the input signal;

a first combiner configured to combine the input signal and the offsetting signal so that the offsetting signal reduces the PAR of the input signal to produce a combined signal;

second electronic circuitry configured to process the combined signal and the offsetting signal; and

a second combiner configured to combine the processed combined signal and the processed offsetting signal.

27. The apparatus in claim 26, wherein the input signal is a multi-carrier signal.

28. The apparatus in claim 26, wherein the offsetting signal is an anti-phase signal.

29. The apparatus in claim 26, wherein the second electronic circuitry includes first and second digital-to-analog converters for converting the combined signal and the offsetting signal, respectively, into analog form, and the second combiner is configured to combine the analog combined signal and the analog offsetting signal to generate an analog combined signal.

30. The apparatus in claim 26, further comprising:

third electronic circuitry configured to process the analog combined signal before transmission.

31. The apparatus in claim 26, further comprising:

third electronic circuitry configured to process in the analog domain the combined signal and the offsetting signal before the combining.

32. The apparatus in claim 26, wherein the first and second digital-to-analog converters have substantially the same characteristics.

33. The apparatus in claim 26, wherein the first and second digital-to-analog converters have substantially different characteristics.

34. Apparatus for reducing a peak-to-average ratio (AR) of an input signal, comprising:

first electronic circuitry configured to receive a digital input signal and to formulate an anti-phase signal for the input signal;

a first combiner configured to combine the input and anti-phase signals to produce a peak-limited digital signal;

a first digital-to-analog converter configured to convert the peak-limited digital signal into a peak-limited analog signal;

a second digital-to-analog converter configured to convert the anti-phase digital signal into an anti-phase analog signal; and

a second combiner configured to combine the peak-limited analog signal and the anti-phase analog signal.

35. The apparatus in claim 34, further comprising:

processing circuitry configured to change a sign of the anti-phase signal or to invert the anti-phase signal before combining the peak-limited and anti-phase analog signals.

36. The apparatus in claim 34, wherein combining the input and anti-phase signals limits the input signal peak value to a threshold associated with a range of the first digital-to-analog converter.

37. The apparatus in claim 36, wherein threshold corresponds to a full scale range of the first digital-to-analog converter such that the peak-limited analog signal does not contribute substantial quantization noise from the conversion in the first digital-to-analog converter to the combined analog signal.

38. The apparatus in claim 37, wherein a dynamic range associated with the digital-to-analog conversion of the input signal using the first and second digital-to-analog converters is greater than using only a single digital-to-analog converter.

39. The apparatus in claim 34, wherein the combining removes distortion caused by peak-limiting the input signal.

40. The apparatus in claim 34, further comprising:

analog processing circuitry configured to perform analog processing on the combined analog signal.

41. The apparatus in claim 34, further comprising:

analog processing circuitry configured to perform analog processing on the peak-limited analog signal and the anti-phase analog signal before the combining.

42. The apparatus in claim 34, further comprising:

a third digital-to-analog converter configured to convert the anti-phase digital signal into an anti-phase analog signal,

wherein the first electronic circuitry is configured to map the anti-phase signal to the second and third digital-to-analog converters and to the first combiner, and

wherein the second and third digital-to-analog converters provide corresponding outputs to the second combiner.

43. The apparatus in claim 34, wherein the first and second digital-to-analog converters have substantially the same characteristics.

44. The apparatus in claim 34, wherein the first and second digital-to-analog converters have different characteristics.