Method and apparatus for an integrated computer and PDA

• US 20030065734A1
• Filed: 09/29/2001
• Published: 04/03/2003
• Est. Priority Date: 09/29/2001
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ramakesavan, Sundaram
• Application Number:
  US09/969,981
• Publication Number:
  US 20030065734A1
• Time in Patent Office: Days
• US Class Current: 709/211
• CPC Class Codes: G06F 1/16 Constructional details or arrangements
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 9/5061 Partitioning or combining of resources

Abstract

A method and apparatus relating to an integrated computer system and PDA is disclosed. In one embodiment, the invention is an apparatus. The apparatus includes a computer system and a PDA. The computer system includes a first processor, a first memory coupled to the first processor, a first display controller coupled to the first processor, and a first display coupled to the first display controller. The computer system selectively includes the PDA. The PDA includes a second processor, a second memory coupled to the second processor, a second display controller coupled to the second processor, and a second display coupled to the second display controller. The second processor is selectively coupled directly to the first processor to operate as a multi-processor system.

Claims

1. An apparatus comprising:

a computer system including;

a first processor;

a first memory coupled to the first processor;

a first display controller coupled to the first processor;

a first display coupled to the first display controller;

and the computer system selectively including PDA, the PDA including;

a second processor;

a second memory coupled to the second processor;

a second display controller coupled to the second processor;

a second display coupled to the second display controller;

and wherein the second processor is selectively coupled directly to the first processor to operate as a multi-processor system.

2. The apparatus of claim 1 further comprising:

a control hub coupled to the first processor and to the first memory and to the first display controller, the control hub to control data flow between the first processor and the first memory, the control hub to control data flow between the first processor and the first display controller, the first memory coupled through the control hub to the first processor, the first display controller coupled through the control hub to the first processor.

3. The apparatus of claim 1 wherein:

the computer system further including a first power supply, the first power supply coupled to each of the first processor, first memory, first display, and first display controller, and the first power supply selectively coupled to each of the second processor, and the second memory;

and the PDA further including a second power supply, the second power supply selectively coupled to each of the second processor, second memory, second display, and second display controller.

4. The apparatus of claim 3 wherein:

the second power supply selectively coupled to the first power supply, the second power supply to receive power from the first power supply.

16. The apparatus of claim 1 wherein:

the second processor is selectively coupled to the first processor through a means for connecting the computer system to the PDA.

17. The apparatus of claim 16 wherein:

the means for connecting is a first connector of the computer system and a second connector of the PDA, the first connector to mate with the second connector.

18. The apparatus of claim 1 wherein:

the second processor is selectively coupled to the first processor through a first connector of the computer system and a second connector of the PDA, the first connector to mate with the second connector, the first connector coupled to the first processor, the second connector coupled to the second processor.

5. A computer system comprising:

a first processor;

a first memory coupled to the first processor;

a first display controller coupled to the first processor;

a first display coupled to the first display controller;

a connector disposed to selectively connect components of a selectively coupled PDA to the first processor.

6. The computer system of claim 5 further comprising:

a first power supply, the first power supply coupled to each of the first processor, first memory, first display, and first display controller, and the first power supply connected to the connector to selectively supply power to the selectively coupled PDA.

7. The computer system of claim 6 wherein:

the connector including a conductor to supply a signal to the selectively coupled PDA to allow the selectively coupled PDA to deactivate components of the selectively coupled PDA.

8. A PDA comprising:

a first processor;

a first memory coupled to the first processor;

a first display controller coupled to the first processor;

a first display coupled to the first display controller;

a connector to selectively connect the first processor directly to a control hub of a computer system.

9. The PDA of claim 8 wherein:

the connector to selectively connect the first memory directly to the control hub of the computer system.

10. The PDA of claim 8 wherein:

the connector to selectively connect the first memory directly to a second processor of the computer system.

11. The PDA of claim 8 wherein:

the connector to selectively connect the first processor directly to a first conductor of the computer system, the first conductor to supply a signal, the processor to disable components of the PDA responsive to the signal.

12. A method comprising:

synchronizing a computer system with a PDA, the PDA directly connected to a processor of the computer system;

detaching the PDA from the computer system;

activating a display of the PDA responsive to the detaching.

13. The method of claim 12 further comprising:

activating a power supply of the PDA responsive to the detaching.

14. The method of claim 12 further comprising:

modifying contents of memory within the PDA;

reattaching the PDA to the computer system, the PDA directly connected to the processor of the computer system;

synchronizing contents of memory within the PDA with a memory of the computer system.

15. The method of claim 14 further comprising:

operating the PDA and the processor of the computer system as a multi-processor computer.

19. An apparatus comprising:

a computer having a processor and a memory coupled to the processor;

a PDA having a processor and a memory coupled to the processor; and

wherein the PDA is selectively coupleable to the computer to allow operation of the processor of the PDA and the processor of the computer as a single multi-processor computer.

20. The apparatus of claim 19 wherein:

the PDA is further selectively coupleable to the computer to allow operation of the memory of the PDA and the memory of the computer as a single memory-mapped set of memory.

21. The apparatus of claim 19 wherein:

the PDA is further selectively coupleable to the computer to allow access to the memory of the PDA and the memory of the computer by the processor of the computer and the processor of the PDA.

22. The apparatus of claim 19 wherein:

the PDA further includes a power supply and the computer further includes a power supply and wherein the PDA is selectively coupleable to the computer to recharge the power supply of the PDA from the power supply of the computer.

23. The apparatus of claim 19 wherein:

the PDA having a display and the computer having a display.

24. The apparatus of claim 23 wherein:

the display of the PDA selectively coupleable to the display of the computer.

25. The apparatus of claim 23 wherein:

the display of the PDA selectively coupleable to a display controller of the computer.

26. The apparatus of claim 23 wherein:

the PDA to disable the display of the PDA responsive to coupling to the computer.