Network adapter with multiple event queues

• US 20030065856A1
• Filed: 04/12/2002
• Published: 04/03/2003
• Est. Priority Date: 10/03/2001
• Status: Abandoned Application

• Current Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Original Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Inventors: Kagan, Michael, Raab, Elazar, Koren, Benjamin, Crupnicoff, Diego, Shachar, Ariel, Shainer, Gilad, Levenvirth, Dafna, Schnitman, Margarita
• Application Number:
  US10/120,418
• Publication Number:
  US 20030065856A1
• Time in Patent Office: Days
• US Class Current: 710/263
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

A method for communication between a network interface adapter and a host processor coupled thereto includes writing information using the network interface adapter to a location in a memory accessible to the host processor. Responsive to having written the information, the network interface adapter places an event indication in an event queue accessible to the host processor. It then asserts an interrupt of the host processor that is associated with the event queue, so as to cause the host processor to read the event indication and, responsive thereto, to process the information written to the location.

Claims

1. A method for communication between a network interface adapter and a host processor coupled thereto, the method comprising:

writing information using the network interface adapter to a location in a memory accessible to the host processor;

responsive to having written the information, placing an event indication, using the network interface adapter, in an event queue accessible to the host processor;

asserting an interrupt of the host processor that is associated with the event queue, so as to cause the host processor to read the event indication and, responsive thereto, to process the information written to the location.

2. A method according to claim 1, wherein writing the information comprises writing completion information regarding a work request submitted by the host processor to the network interface adapter.

3. A method according to claim 2, wherein writing the completion information comprises writing a completion queue element (CQE) to a completion queue.

4. A method according to claim 2, wherein writing the completion information comprises informing the host processor that the network interface adapter has performed at least one of sending an outgoing data packet and receiving an incoming data packet over a packet network responsive to the work request.

5. A method according to claim 1, wherein the information written to the location in the memory belongs to a given information category, and wherein placing the event indication comprises placing the event indication in a particular event queue that corresponds to the given information category, among a plurality of such event queues accessible to the host processor.

6. A method according to claim 5, wherein the given information category is one of a multiplicity of categories of the information written using the network interface adapter, and wherein each of the multiplicity of the categories is mapped to one of the plurality of the event queues, so that placing the event indication comprises placing the event indication in the particular event queue to which the given information category is mapped.

7. A method according to claim 5, wherein the interrupt is one of a multiplicity of such interrupts provided by the host processor, and wherein each of the plurality of the event queues is mapped to one of the multiplicity of the interrupts, so that asserting the interrupt comprises asserting the interrupt to which the particular event queue is mapped.

8. A method according to claim 7, wherein asserting the interrupt comprises mapping the particular event queue uniquely to a specific one of the interrupts, to which none of the other event queues are mapped, and asserting the specific one of the interrupts.

9. A method according to claim 8, wherein asserting the specific one of the interrupts comprises invoking an event handler of the host processor to process the event indication in response to the interrupt, substantially without invoking an interrupt handler of the host processor.

10. A method according to claim 1, and comprising writing context information with respect to the event queue to the memory using the host processor, and wherein placing the event indication in the event queue comprises reading the context information using the network interface adapter, and writing the event indication responsive to the context information.

11. A method for communication between a host channel adapter (HCA) and a host processor coupled thereto, the method comprising:

writing a completion queue element (CQE) using the HCA to a completion queue accessible to the host processor;

responsive to having written the CQE, placing an event indication, using the HCA, in an event queue accessible to the host processor;

asserting an interrupt of the host processor that is associated with the event queue, causing the host processor to read the event indication and, responsive thereto, to process the CQE.

12. A method according to claim 11, wherein writing the CQE comprises informing the host processor that the network interface adapter has executed a work queue element (WQE) responsive to a work request submitted by the host processor to the HCA.

13. A method according to claim 12, wherein informing the host processor comprises notifying an application process that submitted the work request that that the HCA has performed at least one of sending an outgoing data packet and receiving an incoming data packet over a switch fabric responsive to the work request.

14. A method according to claim 12, wherein the WQE belongs to a work queue assigned to the host processor, the work queue having a context indicating the completion queue to which the work queue is mapped, among a plurality of such completion queues maintained by the HCA, and wherein informing the host processor comprises writing the CQE to the completion queue that is indicated by the context of the work queue.

15. A method according to claim 11, wherein writing the CQE comprises writing the CQE to an assigned completion queue among a multiplicity of such completion queues maintained by the HCA, and wherein placing the event indication comprises writing the event indication to a specific event queue to which the assigned completion queue is mapped, among a plurality of such event queues maintained by the HCA.

16. A method according to claim 15, wherein the assigned completion queue is mapped to the specific event queue together with at least one other of the multiplicity of the completion queues.

17. A method according to claim 15, wherein asserting the interrupt comprises asserting a particular interrupt to which the specific event queue is mapped, among two or more such interrupts provided by the host processor.

18. A method according to claim 17, and comprising mapping the plurality of the event queues to respective interrupts provided by the host processor, such that the specific event queue alone is mapped to the particular interrupt.

19. A network interface adapter, comprising:

a network interface, adapted to transmit and receive communications over a network;

a host interface, adapted to be coupled to a host processor, so as to enable the host processor to communicate over the network via the network interface adapter; and

processing circuitry, adapted to write information relating to the communications to a location in a memory accessible to the host processor and responsive to having written the information, to place an event indication in an event queue accessible to the host processor, and further adapted to assert an interrupt of the host processor that is associated with the event queue, so as to cause the host processor to read the event indication and, responsive thereto, to process the information written to the location.

20. An adapter according to claim 19, wherein the information comprises completion information regarding a work request submitted by the host processor to the network interface adapter.

21. An adapter according to claim 20, wherein the completion information comprises a completion queue element (CQE), and wherein the location comprises a completion queue.

22. An adapter according to claim 20, wherein the completion information indicates that the network interface adapter has performed at least one of sending an outgoing data packet and receiving an incoming data packet over the network responsive to the work request.

23. An adapter according to claim 19, wherein the information written to the location in the memory belongs to a given information category, and wherein the processing circuitry is adapted to place the event indication in a particular event queue that corresponds to the given information category, among a plurality of such event queues accessible to the host processor.

24. An adapter according to claim 23, wherein the given information category is one of a multiplicity of categories of the information that the processing circuitry is adapted to write, and wherein each of the multiplicity of the categories is mapped to one of the plurality of the event queues, so that the processing circuitry places the event indication in the particular event queue to which the given information category is mapped.

25. An adapter according to claim 23, wherein the interrupt is one of a multiplicity of such interrupts provided by the host processor, and wherein each of the plurality of the event queues is mapped to one of the multiplicity of the interrupts, so that the processing circuitry asserts the interrupt to which the particular event queue is mapped.

26. An adapter according to claim 25, wherein the particular event queue is mapped uniquely to a specific one of the interrupts, to which none of the other event queues are mapped.

27. An adapter according to claim 26, wherein when the processing circuitry asserts the specific one of the interrupts, an event handler of the host processor is invoked to process the event indication in response to the interrupt, substantially without invoking an interrupt handler of the host processor.

28. An adapter according to claim 19, wherein the processing circuitry is adapted to read context information written to the memory by the host processor with regard to the event queue, and to write the event indication responsive to the context information.

29. A host channel adapter (HCA), comprising:

a network interface, adapted to transmit and receive data packets over a switch fabric;

a host interface, adapted to be coupled to a host processor, so as to enable the host processor to communicate over the fabric via the HCA; and

processing circuitry, adapted to write a completion queue element (CQE) to a completion queue accessible to the host processor and responsive to having written the CQE, to place an event indication in an event queue accessible to the host processor, and further adapted to assert an interrupt of the host processor that is associated with the event queue, causing the host processor to read the event indication and, responsive thereto, to process the CQE.

30. An adapter according to claim 29, wherein the processing circuitry is adapted to write the CQE so as to inform the host processor that the network interface adapter has executed a work queue element (WQE) responsive to a work request submitted by the host processor to the HCA.

31. An adapter according to claim 30, wherein the CQE is arranged to inform an application process that submitted the work request that that the HCA has performed at least one of sending an outgoing data packet and receiving an incoming data packet over the switch fabric responsive to the work request.

32. An adapter according to claim 30, wherein the WQE belongs to a work queue assigned to the host processor, the work queue having a context indicating the completion queue to which the work queue is mapped, among a plurality of such completion queues maintained by the processing circuitry, and wherein the processing circuitry is adapted to write the CQE to the completion queue that is indicated by the context of the work queue.

33. An adapter according to claim 29, wherein the processing circuitry is adapted to write the CQE to an assigned completion queue among a multiplicity of such completion queues that it maintains, and to write the event indication to a specific event queue to which the assigned completion queue is mapped, among a plurality of such event queues that it maintains.

34. An adapter according to claim 33, wherein the assigned completion queue is mapped to the specific event queue together with at least one other of the multiplicity of the completion queues.

35. An adapter according to claim 33, wherein the processing circuitry is adapted to assert a particular interrupt to which the specific event queue is mapped, among two or more such interrupts provided by the host processor.

36. An adapter according to claim 35, wherein the plurality of the event queues are mapped to respective interrupts provided by the host processor, such that the specific event queue alone is mapped to the particular interrupt.

37. An adapter according to claim 29, wherein the host interface is configured to couple the processing circuitry to the host processor via a parallel bus, and wherein the processing circuitry is adapted to assert the interrupt by sending an interrupt message over the bus.

38. An adapter according to claim 29, wherein the host processor has one or more interrupt pins, and wherein the host interface comprises one or more input/output pins, adapted to be coupled to the interrupt pins of the host processor so as to enable the processing circuitry to assert the interrupt therethrough.