Distributed peer-to-peer communication for interconnect busses of a computer system

• US 20030065868A1
• Filed: 09/29/2001
• Published: 04/03/2003
• Est. Priority Date: 09/29/2001
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Riley, Dwight D.
• Granted Patent: US 7,028,132 B2
• Time in Patent Office: Days
• US Class Current: 710/313
• CPC Class Codes: G06F 13/423 with synchronous protocol

Abstract

Distributed peer-to-peer transactions are defined on an interconnect bus of a computer system according to an interconnect protocol. The transactions contain a completer device attribute data and a self-defining payload data. The transaction is identified as a peer-to-peer transaction by a command or an attribute data in the transaction. The transaction can be routed across a hierarchy of interconnect bus segments using the completer device address data. A handle can be used by an operating system of the computer system to indicate permission for the peer-to-peer transaction. Address information in a completer device address space can be provided within the peer-to-peer transaction or by a completer device driver for use by the completer device in processing the peer-to-peer transaction.

Claims

1. A method of providing a distributed peer-to-peer transaction between a requester device and a completer device, the method comprising the steps of:

inserting a completer device address data into the distributed peer-to-peer transaction;

inserting a self-defining payload data into a data phase of the distributed peer-to-peer transaction; and

sending the distributed peer-to-peer transaction over an interconnect bus of a computer system according to an interconnect protocol.

2. The method of claim 1, further comprising the step of:

inserting a peer-to-peer command into a command phase of the distributed peer-to-peer transaction.

3. The method of claim 1, further comprising the step of:

setting an attribute in an attribute phase of the distributed peer-to-peer transaction, the attribute indicating the distributed peer-to-peer transaction is a peer-to-peer transaction.

4. The method of claim 1, the step of inserting a completer device attribute data comprising the step of:

inserting the completer device address data into the address phase of the distributed peer-to-peer transaction.

5. The method of claim 1, the step of inserting a completer device attribute data comprising the step of:

inserting a bus identifier associated with the completer device; and

inserting a device identifier associated with the completer device.

6. The method of claim 5, the step of inserting a completer device attribute data further comprising the step of:

inserting a function identifier associated with the completer device.

7. The method of claim 1, further comprising the step of:

obtaining the completer device address data from a device driver of the operating system associated with the requester device.

8. The method of claim 1, wherein the interconnect protocol is the PCI-X interconnect protocol.

9. The method of claim 1, the step of inserting a self-defining payload data into a data phase of the distributed peer-to-peer transaction comprising the step of:

setting an attribute in the attribute phase to indicate the presence of a self-defining payload data in the data phase.

10. The method of claim 1, further comprising the step of:

routing the distributed peer-to-peer transaction across a hierarchy of interconnect bus segments using the completer device address data.

11. The method of claim 1, further comprising the step of:

obtaining a handle from a device driver of an operating system associated with the requester device,

wherein the handle indicates permission by the operating system for peer-to-peer transactions between the requester device and the completer device.

12. The method of claim 11, further comprising the step of:

inserting the handle into an attribute phase of the distributed peer-to-peer transaction.

13. The method of claim 11, the step of inserting a completer device attribute data comprising the step of:

inserting the handle in the data phase of the distributed peer-to-peer transaction.

14. The method of claim 11, the step of obtaining a handle from a device driver of an operating system comprising the step of:

requesting the handle from a device driver associated with the requester prior to sending the distributed peer-to-peer transaction.

15. The method of claim 11, the step of obtaining a handle from a device driver of an operating system comprising the step of:

requesting the handle from a device driver associated with the completer upon receiving the distributed peer-to-peer transaction.

16. The method of claim 1, further comprising the step of:

inserting an address in a completer device address space into the data phase of the distributed peer-to-peer transaction.

17. The method of claim 1, the self-defining payload data comprising:

an information field; and

a definition field, the definition field providing structure and content definition data for the information field.

18. A computer system comprising:

a central processing unit connected to a host bus;

a random access memory connected to a system memory bus;

an interconnect bus operating according to an interconnect protocol;

a core logic chip coupled as a first interface bridge between the host bus and the system memory bus, as a second interface bridge between the host bus and the interconnect bus, and as a third interface bridge between the system memory bus and the interconnect bus; and

a first device coupled to the interconnect bus, the first device operating according to an interconnect protocol, the first device adapted to provide a plurality of phases in an interconnect transaction, the interconnect transaction comprising;

a completer device address data; and

a self-defining payload data in a data phase of the interconnect transaction.

19. The computer system of claim 18, the interconnect transaction further comprising:

a command, the command contained in a first phase of the interconnect transaction, the command identifying the interconnect transaction as a peer-to-peer interconnect transaction.

20. The computer system of claim 18, the interconnect transaction further comprising:

an attribute phase, the attribute phase identifying the interconnect transaction as a peer-to-peer interconnect transaction.

21. The computer system of claim 18,

wherein the interconnect bus is a PCI-X bus, and

wherein the command is issued on a C/BE# portion of the PCI-X bus.

22. The computer system of claim 18,

wherein the completer device address data is inserted into an address phase of the interconnect transaction.

23. The computer system of claim 18,

wherein the interconnect bus is a PCI-X bus.

24. The computer system of claim 18, the self-defining payload data comprising:

an information field; and

a definition field, the definition field providing structure and content definition data for the information field.

25. The computer system of claim 18, the interconnect transaction further comprising:

an attribute phase, the attribute phase indicating the presence of a self-defining payload data in the data phase.

26. The computer system of claim 18, further comprising:

an operating system for controlling the central processing unit, the operating system granting permission for the interconnect transaction.

27. The computer system of claim 26, further comprising:

a requester device driver coupled to the operating system and the requester device, the requester device driver obtaining a handle from the operating system, the handle indicating permission for the interconnect transaction with the completer device, the requester device driver passing the handle to the requester device, the handle inserted into the data phase of the interconnect transaction by the requester device.

28. The computer system of claim 26, further comprising:

a completer device driver coupled to the operating system and the completer device, the completer device driver obtaining a handle from the operating system, the handle indicating permission for the interconnect transaction with the completer device, the completer device driver passing the handle to the completer device upon receipt of the interconnect transaction by the completer device.

29. The computer system of claim 28, wherein the completer device requests the handle from the completer device driver.

30. The computer system of claim 18, the interconnect transaction further comprising:

an address in a completer device address space, the address inserted into the data phase of the interconnect transaction.

31. The computer system of claim 18,

wherein the interconnect bus is organized into a hierarchy of interconnect bus segments, the hierarchy of interconnect bus segments coupled by interconnect bus bridges, and

wherein the interconnect transaction is routed between interconnect bus segments using the completer device address data.

32. The computer system of claim 18, further comprising:

a completer device driver coupled to an operating system of the computer system and the completer device, the completer device driver providing an address in a completer device address space corresponding to the requester device for use by the completer device in processing interconnect transactions from the requester device.

33. A computer system comprising:

a processor;

a random access memory coupled to the processor;

an interconnect bus coupled to the processor and the random access memory, the interconnect bus operating according to an interconnect protocol;

a requester device coupled to the interconnect bus, the requester device adapted to generate interconnect bus transactions to a completer device coupled to the interconnect bus, the requester device and the completer device operating according to the interconnect protocol, the transactions comprising;

means for indicating a completer device;

a payload data;

means for converting the payload data into a completer device format.

34. The computer system of claim 33, the means for indicating a completer device comprising:

means for routing the interconnect bus transaction from the requester device to the completer device across a hierarchy of bus segments.

35. The computer system of claim 33, the payload data having a transaction format, the means for converting comprising:

means for interpreting the transaction format.

36. The computer system of claim 33, the payload data having an internal structure, the means for converting comprising:

means for interpreting the internal structure of the payload data.

37. The computer system of claim 33, the payload data having a type, the means for converting comprising:

means for interpreting the type of the payload data.