Method and apparatus for reordering memory requests for page coherency

• US 20030065897A1
• Filed: 09/28/2001
• Published: 04/03/2003
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Navale, Aditya, Sadowsky, Jonathan B.
• Granted Patent: US 6,898,679 B2
• Time in Patent Office: Days
• US Class Current: 711/165
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0859 with reload from main memory

Abstract

A method and apparatus for reordering memory requests for page coherency. Various data streams are frequently found in separate areas of physical memory (i.e. each data stream is found in a separate memory “page”). Because these requests from different streams become intermixed, a certain amount of latency results from the resulting page “breaks.” These page breaks occur when consecutive requests are from different data streams, requiring accesses to different memory pages. When several separate streams of data are requested by a client, page coherency between requests diminishes. A reordering device regains lost page coherency, thereby reducing the amount of latency and increasing overall system performance.

Claims

1. A method of reordering data requests, comprising:

inserting each of said requests into one of a plurality of buffers, each buffer having an associated physical memory page identification tag;

determining if a flush condition is present; and

removing said requests from said buffers during a flush based on said physical memory page identification tag.

2. The method of claim 1 wherein said requests are for data streams residing in separate physical memory pages.

3. The method of claim 2 further comprising:

marking said requests with a physical memory page identification tag which corresponds to one of said physical memory pages from which said data streams reside.

4. The method of claim 3 wherein each of said requests marked with a physical memory page identification tag is inserted in said buffers assigned with a corresponding page ID.

5. The method of claim 4 wherein said buffers are First-In First-Out buffer devices (FIFOs).

6. The method of claim 5 wherein said flush occurs in a round-robin fashion, such that each of said buffers, in succession, removes said requests.

7. The method of claim 6 wherein, during said flush, all of said requests marked with a first physical memory page identification tag are removed from said buffer with corresponding first physical memory page identification tag prior to removing said requests with a second physical memory page identification tag in said buffer with corresponding second page ID.

8. The method of claim 7 further comprising:

marking said requests inserted in said buffers with one of a plurality of flush class identification tags.

9. The method of claim 8 wherein said requests marked with the same flush class identification tag are associated with a flush class.

10. The method of claim 9 wherein said requests of a flush class are removed together from said buffers during said flush.

11. A memory request reordering system comprising:

a client to send requests to memory;

a reordering device coupled to said client to receive said requests; and

a memory arbiter coupled to said reordering device to selectively remove requests from said reordering device when a flush condition is present.

12. The reordering system of claim 11 wherein said data requests are for data streams residing in separate physical memory pages.

13. The reordering system of claim 12 wherein said data requests are marked with a physical memory page identification tag which corresponds to one of said physical memory pages from which said data streams reside.

14. The reordering system of claim 13 wherein each of said requests marked with a physical memory page identification tag is inserted in said buffer assigned with a corresponding physical memory page identification tag.

15. The reordering system of claim 14 wherein said requests are removed from said buffer during a flush based on said physical memory page identification tag.

16. The reordering system of claim 15 wherein said buffers are emptied in a “

round-robin”

fashion, such that each of said buffers, in succession, removes said requests.

17. The reordering system of claim 16 wherein said requests inserted into buffers are marked with one of a plurality of flush class identification tags.

18. The reordering system of claim 17 wherein said requests marked with the same flush class identification tag are associated with a flush class.

19. The reordering system of claim 18 wherein said requests of a flush class are removed together from said buffers during said flush.

20. A cache memory system comprising:

a reordering device to receive a number of out-of-order request and to reorder said data requests.

21. The cache memory system of claim 20 wherein said data requests are data stream requests.

22. The cache memory system of claim 21 wherein said reordering device is part of a cache memory in said cache memory system.

23. The cache memory system of claim 22 further comprising:

a memory arbiter coupled to said cache memory to receive said reordered data requests; and

a client coupled to said cache memory to request data from at least one of said data streams.

24. The cache memory system of claim 23 wherein said reordering device includes at least one buffer to hold data requests.

25. The cache memory system of claim 24 wherein said buffers are First-In First-Out buffer devices (FIFOs).

26. The cache memory system of claim 25 wherein each buffer is to store data requests from a single memory page.