Progressive CPU sleep state duty cycle to limit peak power of multiple computers on shared power distribution unit

• US 20030065961A1
• Filed: 09/29/2001
• Published: 04/03/2003
• Est. Priority Date: 09/29/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Koenen, David J.
• Granted Patent: US 6,904,534 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

A method and apparatus for distributing power to a plurality of computers in a network. A power management system including a feed-back mechanism, is employed to monitor power consumptions of the plurality of computers. Should the overall power consumption reach a threshold, the power management system instructs the microprocessors in the plurality of computers to enter into a lower power state, such as a sleep state, for a certain duration, thus lowering overall power.

Claims

1. A computer system, comprising:

a power management system coupled to a power source; and

a plurality of computers, including a plurality of microprocessors, the plurality of computers are coupled to the power management system;

wherein the power management system monitors a plurality of current demands of the computers, and

wherein the power management system instructs the plurality of microprocessors to enter into a certain lower power state for a certain duration responsive to changing current demands of the plurality of computers.

2. The computer system of claim 1, wherein the microprocessor is a Pentium-type processor.

3. The computer system of claim 2, wherein the lower power state is a sleep state.

4. The computer system of claim 3, wherein the plurality of microprocessors can respond to snoops and interrupts.

5. The computer system of claim 3, wherein the sleep state is a stop-grant state.

6. The computer system of claim 1, wherein the certain duration is a power down duty cycle.

7. The computer system of claim 1, wherein the plurality of computers include a plurality of monitors for measuring the plurality of current demands.

8. The computer system of claim 1, wherein the power management system instructs the plurality of microprocessors to enter into a certain lower power state for certain duration by a command encoded in power lines from the power management system to the plurality of computers.

9. The computer system of claim 1, wherein the power management system instructs the plurality of microprocessors to enter into a certain lower power state for certain duration by a command over a data link.

10. The computer system of claim 1, wherein the power management system is not included in one of the plurality of computers.

11. The computer system of claim 1, wherein the power management system is included in one of the plurality of computers.

12. The computer system of claim 1, wherein the changing current demands is a cumulative current demand of the plurality of computers.

13. A method for providing power to a plurality of computers, comprising the steps of:

measuring current demands for the plurality of computers;

calculating a total current demand; and

placing each computer in a lower power state for a time certain should the total current demand exceed a threshold.

14. The method of claim 13, wherein the plurality of computers include Pentium-type microprocessors.

15. The method of claim 13, wherein the lower power state is a sleep state.

16. The method of claim 15, further comprising the step of responding to snoops and interrupts.

17. The method of claim 16, wherein the sleep state is a stop-grant state.

18. The method of claim 13, wherein placing each computer in a sleep state includes an insertion of a STPCLK signal.

19. The method of claim 13, wherein the time certain is a power down duty cycle.

20. The method of claim 19, wherein the power down duty cycle is less than 90%.