Processor device equipped with flash memory and debugger apparatus

• US 20030065984A1
• Filed: 09/10/2002
• Published: 04/03/2003
• Est. Priority Date: 09/10/2001
• Status: Abandoned Application

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Takeda, Kazuyoshi, Kashine, Takashi
• Application Number:
  US10/241,002
• Publication Number:
  US 20030065984A1
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written

Abstract

A processor apparatus (microcomputer) 1 is equipped with a flash memory 17 which performs processing according to a processing program and rewriting for the flash memory. The flash memory-equipped processor apparatus comprises a mode switch register 18a that sets a normal mode that performs operations according to a processing program (application program) AP and a self-rewriting mode that performs rewriting operations for the flash memory during execution of the processing program. When processes in a self-rewriting mode are programmed in the processing program AP, a control device (CPU) 2 sets, during execution of the processing program AP, the mode switch register 18a to the self-rewriting mode, and performs a rewriting operation for the flash memory 17 according to a rewriting program (self-rewriting program) WP.

Claims

1. A flash memory-equipped processor apparatus, which performs processing according to a processing program and rewriting for a flash memory, the flash memory-equipped processor apparatus comprising:

a mode switch register that sets a normal mode that performs processing according to the processing program and a self-rewiting mode that performs rewriting for the flash memory during execution of the processing program;

a rewriting program that programs a writing process for the flash memory; and

a control device that executes the processing program,

wherein the control device sets, during execution of the processing program, the mode switch register to the self-rewriting mode, and performs rewriting for the flash memory according to the rewriting program.

2. A flash memory-equipped processor apparatus according to claim 1, wherein the flash memory is divided into a plurality of sectors, the control device writes test data in a specified sector of the flash memory after the mode switch register is set to the self-rewriting mode, and after writing performs rewriting for the flash memory when data stored in the specified sector is in accordance with the test data.

3. A flash memory-equipped processor apparatus according to claim 1, further comprising a memory device that stores data, wherein the processing program programs a process of writing verification data in a predetermined region of the memory device before processing in the self-rewriting mode,

the control device writes verification data in a predetermined region of the memory device before setting the mode switch register to the self-rewriting mode according to the processing program, and after setting the mode switch register to the self-rewriting mode, performs rewriting for the flash memory when data stored in the predetermined region of the memory device accords with the verification data.

4. A flash memory-equipped processor apparatus according to claim 1, wherein the flash memory is divided into a plurality of sectors, wherein the sectors have rewriting number counters that set rewriting numbers,

the control device reads out a rewriting number set at the rewriting number counter of the sector to be rewritten after setting the mode switch register to the self-rewriting mode, and performs rewriting of the sector to be rewritten when the rewriting number is at a rewriting limit number or lower, and performs rewriting of a sector different from the sector to be rewritten when the rewriting number exceeds over the rewriting limit number.

5. A flash memory-equipped processor apparatus according to claim 1, further comprising a first oscillation device that generates a first clock having a constant frequency, and a second oscillation device that generates a second clock, wherein the control device calculates a specified cycle with the second clock based on a constant time formed from the first clock.

6. A flash memory-equipped processor apparatus according to claim 1, further comprising debugger apparatus that debugs the flash memory-equipped processor apparatus, wherein, when a start of execution of the rewriting program is detected during debugging, the execution of the rewriting program is not stopped halfway through thereof.

7. A flash memory-equipped processor apparatus according to claim 6, wherein, when the rewriting program is executed during debugging, information indicating that rewriting is performed at the flash memory is output.

8. A method of operating a computer processing system having a flash memory and a central processing unit (CPU), said method comprising:

a.) in a normal mode, using the CPU to execute instructions from an application program stored in the flash memory

b.) storing new write data in a volatile memory and, in response thereto, setting a mode switch register to a self-rewriting mode;

c.) transferring the new write data to a flash control register;

d.) rewriting a sector of the flash memory with the new write data; and

e.) controlling the CPU so that it returns to executing instructions from the application program after the flash memory has been rewritten.