Scan flip-flop and semiconductor integrated circuit device
First Claim
1. A scan flip-flop having a normal operation and a scan test operation, the scan flip-flop comprising:
- a master latching circuit that latches a data input in response to a normal clock in the normal operation and latches a scan-in signal in response to a first scan clock in the scan test operation;
a slave latching circuit that provides the latched data input from the master latching circuit in synchronsim with the normal clock in the normal operation and provides the latched scan-in signal from the master latching circuit in synchronsim with a second scan clock in the scan test operation; and
a clock circuit coupled to receive a first switching signal that sets the master latching circuit and slave latching circuit to operate as a positive flip-flop or a negative flip-flop in the normal operation.
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Accused Products
Abstract
A scan flip-flop (100A) that may operate as a positive flip-flop or a negative flip-flop in a normal operating mode has been disclosed. Scan flip-flop (100A) may include a master latching circuit (11), a slave latching circuit (12), and a clock circuit (13A). Clock circuit (13A) may receive a signal (XA), a control signal (control), and a mode signal (SCN). Signal (XA) may select between a positive flip-flop operation and a negative flip-flop operation when in a normal operating mode. Mode signal (SCN) may select between a normal operating mode and a scan test mode. Control signal (control) may disable signal (XA) so that scan flip-flop (100A) may operate in a known mode, such as a positive flip-flop, regardless as to the value of signal (XA). Scan flip-flop (100A) may reduce logic gates in clock lines which may be required in a conventional approach.
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Citations
20 Claims
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1. A scan flip-flop having a normal operation and a scan test operation, the scan flip-flop comprising:
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a master latching circuit that latches a data input in response to a normal clock in the normal operation and latches a scan-in signal in response to a first scan clock in the scan test operation;
a slave latching circuit that provides the latched data input from the master latching circuit in synchronsim with the normal clock in the normal operation and provides the latched scan-in signal from the master latching circuit in synchronsim with a second scan clock in the scan test operation; and
a clock circuit coupled to receive a first switching signal that sets the master latching circuit and slave latching circuit to operate as a positive flip-flop or a negative flip-flop in the normal operation. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A scan flip-flop having a normal operation for operating as a normal flip-flop receiving data input and a scan test operation for operating as a flip-flop receiving a scan-in signal as a test pattern signal and a first and second scan clock as test clocks, the scan flip-flop including:
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a master latching circuit that temporarily holds the data input in response to a normal clock in the normal operation and that temporarily holds the scan-in signal in response to the first scan clock in the scan test operation;
a slave latching circuit that outputs the temporarily held data input in the master latching circuit in response to the normal clock in the normal operation and outputs the temporarily held scan-in signal in the master latching circuit in response to the second scan clock in the scan test operation; and
a clock circuit coupled to receive an externally applied first switching signal that configures the master latching circuit and slave latching circuit into a positive flip-flop that outputs the temporarily held data input in response to a rising edge of the normal clock or a negative flip-flop that outputs the temporarily held data input in response to a falling edge of the normal clock, the clock circuit also being coupled to receive an externally applied second switching signal that switches the master latching circuit and slave latching circuit into the normal operation or the scan test operation. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A semiconductor integrated circuit, comprising:
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a scan flip-flop having a normal mode and a scan test mode, the scan flip-flop coupled to receive a normal data input, a scan data input, and a first clock signal and providing a normal data output and a scan data output;
a clock circuit coupled to receive a normal clock signal, a first control signal, and a scan test signal and providing the first clock signal;
the first control signal having a positive flip-flop logic level and a negative flip-flop logic level; and
the scan test signal having a scan test mode logic level and a normal mode logic level wherein the scan flip-flop operates as a positive flip-flop when the first control signal has the positive flip-flop logic level and the scan test signal has the normal mode logic level and operates as a negative flip-flop when the first control signal has the negative flip-flop logic level and the scan test signal has the normal mode logic level. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification