×

Scan flip-flop and semiconductor integrated circuit device

  • US 20030066002A1
  • Filed: 09/04/2002
  • Published: 04/03/2003
  • Est. Priority Date: 09/05/2001
  • Status: Active Grant
First Claim
Patent Images

1. A scan flip-flop having a normal operation and a scan test operation, the scan flip-flop comprising:

  • a master latching circuit that latches a data input in response to a normal clock in the normal operation and latches a scan-in signal in response to a first scan clock in the scan test operation;

    a slave latching circuit that provides the latched data input from the master latching circuit in synchronsim with the normal clock in the normal operation and provides the latched scan-in signal from the master latching circuit in synchronsim with a second scan clock in the scan test operation; and

    a clock circuit coupled to receive a first switching signal that sets the master latching circuit and slave latching circuit to operate as a positive flip-flop or a negative flip-flop in the normal operation.

View all claims
  • 4 Assignments
Timeline View
Assignment View
    ×
    ×