Semiconductor package

• US 20030067070A1
• Filed: 09/16/2002
• Published: 04/10/2003
• Est. Priority Date: 10/05/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwon, Heung-Kyu, Cho, Tae-Je, Kim, Min-Ha, Oh, Se-Yong
• Granted Patent: US 6,952,050 B2
• Time in Patent Office: Days
• US Class Current: 257/706
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/433 Auxiliary members in containers characterised by their shape, e.g. pistons
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16251 Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

Abstract

Semiconductor packages are provided to prevent a chip, such as a central processing unit (CPU) chip, from being degraded due to hot spot heat generated during the operation of the chip and absorbs thermomechanical stresses in interfaces between the chip, a thermal interface material (TIM) and a lid. The chip is electrically connected, e.g., flip-chip bonded, to a package substrate. The lid is thermally connected to and disposed over a back surface of the chip with the TIM interposed therebetween. A heat dissipation means adjacent the TIM is also located between the lid and the chip to prevent the hot spot effect.

Claims

1. A semiconductor package comprising:

a chip having an active surface and an outside surface, the chip having a plurality of electrode bumps formed on the active surface thereof;

a package substrate having an upper surface and a lower surface opposite the upper surface, the chip being electrically connected to the upper surface of the substrate;

a lid thermally connected to and disposed over the upper surface of the chip for emitting heat generated from the chip;

a thermal interface material (TIM) interposed between the chip and the lid for transferring heat generated from the chip to the lid; and

a heat dissipation means also interposed between the chip and the lid for dissipating heat, the heat dissipation means adjacent the TIM.

2. The semiconductor package of claim 1, wherein the heat dissipation means is selected from the group consisting of diamond, graphite and synthesis silicon.

3. The semiconductor package of claim 2, wherein the heat dissipation means is a heat dissipation cover formed around the outside surface of the chip except the active surface of the chip.

4. The semiconductor package of claim 3, wherein the TIM is solder, further comprising an under barrier metal (UBM) formed between a bottom surface of the lid and a lower surface of the heat dissipation cover.

5. The semiconductor package of claim 2, wherein the heat dissipation means is a heat dissipation layer formed on the lower surface of the lid opposite the TIM.

6. The semiconductor package of claim 5, further comprising:

an UBM formed between the lid and the heat dissipation layer.

7. The semiconductor package of claim 6, wherein the lid is made of aluminum and the UBM is formed by an anodizing method.

8. The semiconductor package of claim 6, wherein the lid is made of Cu, CuW, AlSiC or CuMo and the UBM is formed by a plating method.

9. The semiconductor package of claim 6, wherein the lid is made of Si, SiO₂, Al₂O₃, AlN or BeO and the UBM is formed by a sputtering or an evaporation method.

10. The semiconductor package of claim 6, wherein the TIM is solder, and wherein the UBM is formed on a heat dissipation layer of the lid and the back surface of the CPU chip.

11. The semiconductor package of claim 1, wherein a space between the lid and the substrate is filled with a filling material.

12. The semiconductor package of claim 11, wherein the flip-chip bonded chip and the substrate is filled with the epoxy resin provided by an under-filling method.

13. The semiconductor package of claim 1, further comprising external connection terminals extending from the lower surface of the substrate and electrically connected to the chip.

14. The semiconductor package of claim 1, wherein the chip is electrically connected to the substrate using a flip chip technology.

15. The semiconductor package of claim 1, wherein the heat dissipation means has a thermal conductivity of about 1000W/mk or more and comprises a material having a coefficient of thermal expansion of about 4.0 or less