Current-controlled CMOS circuit using higher voltage supply in low voltage CMOS process
First Claim
1. A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising:
- first circuitry implemented using current-controlled complementary metal-oxide semiconductor C3MOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, the first circuitry being configured to process a first signal having a first frequency; and
second circuitry coupled to the first circuitry and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, wherein, the first circuitry is coupled to a first power supply voltage and the second circuitry is coupled to a second power supply voltage that is different than the first power supply voltage.
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Abstract
Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.
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Citations
20 Claims
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1. A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, comprising:
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first circuitry implemented using current-controlled complementary metal-oxide semiconductor C3MOS logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, the first circuitry being configured to process a first signal having a first frequency; and
second circuitry coupled to the first circuitry and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, wherein, the first circuitry is coupled to a first power supply voltage and the second circuitry is coupled to a second power supply voltage that is different than the first power supply voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A metal-oxide-semiconductor field-effect transistor (MOSFET) circuit comprising:
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a first circuit implemented using current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals, the first circuit receiving a first power supply voltage;
a second circuit coupled to the first circuit and implemented using conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current is dissipated, the second circuit receiving a second power supply voltage that is lower in magnitude than the first power supply voltage; and
a third circuit coupled to the second circuit and implemented using C3MOS logic, the third circuit receiving the first power supply voltage. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A method for processing high speed signals using silicon complementary metal-oxide-semiconductor (CMOS) technology, the method comprising:
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receiving the high speed signal at a first circuit that uses current-controlled complementary metal-oxide semiconductor (C3MOS) logic wherein logic levels are signaled by current steering in one of two or more branches in response to differential input signals;
powering the first circuit using a first power supply voltage;
converting the high speed signal into a lower frequency signal;
processing the lower frequency signal by a second circuit that uses standard CMOS logic wherein substantially zero static current is dissipated; and
powering the second circuit using a second power supply voltage that is smaller in magnitude than the first power supply voltage. - View Dependent Claims (19, 20)
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Specification