Display device and semiconductor device

• US 20030067434A1
• Filed: 10/02/2002
• Published: 04/10/2003
• Est. Priority Date: 10/03/2001
• Status: Active Grant

• Current Assignee: HannStar Display Corporation
• Original Assignee: NEC Corporation
• Inventors: Haga, Hiroshi, Takatori, Kenichi, Asada, Hideki
• Granted Patent: US 7,259,740 B2
• Time in Patent Office: Days
• US Class Current: 345/98
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2300/08 Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/06 Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04

Abstract

A display device of high definition, multiple colors and low power consumption includes a display panel having a pixel section in which pixels are arrayed in the form of a matrix at the cross points of a plurality of data lines and a plurality of scanning lines, a scanning circuit for applying voltage sequentially to the plurality of scanning lines, and a data-line driver, which receives display data supplied by a host device, for applying signals corresponding to the display data to the plurality of data lines. Provided external to the display panel is a controller IC having a display memory for storing display data corresponding to the pixel section, an output buffer for reading data out of the display memory and outputting this data to the display panel, and a controller for controlling the display memory and output buffer and communication with the host device. The display panel is provided with a digital/analog converter, which forms part of the data-line driver, for converting display data represented by a digital signal to an analog signal. The width of a bus for data transfer between the controller IC and data-line driver of the display panel is such that data of a greater number of bits is transferred in parallel by a single transfer than is transferred by the bus between the controller and the host device. This allows the operating frequency of the data-line driver to be reduced.

Claims

1. A display device comprising:

a display panel having a display area in which a plurality of pixels are arrayed in the form of a matrix at cross points of a plurality of data lines and a plurality of scanning lines;

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines;

a data-line driver circuit for receiving display data supplied by a host device, and for applying signals corresponding to the display data to the plurality of data lines;

a controller IC provided externally of said display panel, said controller IC including a display memory for storing display data, an output buffer for reading data out of said display memory and for outputting the data to said display panel, and a controller for controlling said display memory and said output buffer as well as managing communication and control with the host device; and

a digital/analog converter circuit, provided on said display panel and forming part of said data-line driver circuit, for converting display data represented by a digital signal transferred from said controller IC, to an analog signal;

wherein width of a bus for data transfer between said controller IC and said display panel is such that data of a greater number of bits is transferred in parallel by a single transfer than is transferred by a bus between said controller and the host device.

6. The device according to claim 1, wherein said display panel includes a selector circuit, to which outputs from said digital/analog converter circuit are supplied, for connecting the outputs to a group of data lines.

7. The device according to claim 1, wherein said display panel includes a level shifter for level-shifting a signal amplitude specified by a power-supply voltage of said controller IC, to a high-voltage on the side of said display panel.

8. The device according to claim 1, wherein said display panel includes a serial/parallel converter circuit for converting serial data to parallel data, said the parallel data output from said serial/parallel converter circuit being supplied to said digital/analog converter circuit.

9. The device according to claim 1, wherein said scanning-line driver circuit is provided on both sides of said display area, and a timing-buffer for supplying said data-line driver circuit with a clock is provided on both sides of said display area.

10. The device according to claim 1, wherein said display panel is provided with a circuit, which forms part of said data-line driver circuit, for converting voltage to current, said circuit driving the data lines by current.

11. The device according to claim 1, wherein said display area comprises at least a liquid crystal device.

12. The device according to claim 1, wherein said display area comprises at least an organic electroluminescent device.

13. The device according to claim 1, wherein transistors, composing said display area, said data-line driver circuit and said scanning-line driver circuit, have identical structure with regard to gate insulating film, the film thickness of gate insulating films of the transistors being the same within variances dependent on a fabrication process.

14. The device according to claim 1, wherein transistors, formed on said display panel and composing a peripheral circuit including said data-line driver circuit and said scanning-line driver circuit, are formed by a fabrication process identical with that for forming transistors composing pixel switches of the display area formed on said display panel;

and

film thickness of gate insulating films of the transistors of the peripheral circuit that includes said data-line driver circuit and said scanning-line driver circuit are set to be the same and in conformity with film thickness of gate insulating film of a transistor driven by high voltage.

59. The device according to claim 13, wherein said transistors comprise polysilicon thin-film transistors.

2. A display device comprising:

a display panel having a display area in which a plurality of pixels are arrayed in the form of a matrix at cross points of a plurality of data lines and a plurality of scanning lines;

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines;

a data-line driver circuit for receiving display data supplied by a host device, and for applying signals corresponding to the display data to the plurality of data lines;

a controller IC provided externally of said display panel, said controller IC including a display memory for storing display data, an output buffer for reading data out of said display memory and for outputting the data to said display panel, and a controller for controlling said display memory and said output buffer as well as managing communication and control with the host device; and

a voltage-to-current converting circuit, provided on said display panel and forming part of said data-line driver circuit, for converting display data represented by a digital signal transferred from said controller IC, to an analog current signal;

wherein width of a bus for data transfer between said controller IC and said display panel is such that data of a greater number of bits is transferred in parallel by a single transfer than is transferred by a bus between said controller and the host device.

74. The device according to claim 2, wherein said display panel includes a level shifter for level-shifting a signal amplitude specified by a power-supply voltage of said controller IC, to a high-voltage on the side of said display panel.

3. A display device comprising:

a display panel having a display area in which a plurality of pixels are arrayed in the form of matrix at cross points of a plurality of data lines and a plurality of scanning lines;

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines; and

a data-line driver circuit for receiving display data supplied by a host device, and for applying signals corresponding to the display data to the plurality of data lines,

said display panel further including, at least,

a display memory for storing the display data; and

a digital/analog converter circuit, for converting display data represented by a digital signal read out of said display memory and transferred thereto, to an analog signal.

73. The device according to claim 3, wherein said display panel includes a selector circuit, to which outputs from said digital/analog converter circuit are supplied, for connecting the outputs to a group of data lines.

75. The device according to claim 3, wherein said display panel includes a serial/parallel converter circuit for converting serial data to parallel data, said the parallel data output from said serial/parallel converter circuit being supplied to said digital/analog converter circuit.

4. A display device comprising:

a display panel having a display area in which a plurality of pixels are arrayed in the form of matrix at cross points of a plurality of data lines and a plurality of scanning lines;

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines; and

a data-line driver circuit for receiving display data supplied by a host device, and for applying signals corresponding to the display data to the plurality of data lines;

a display memory provided on said display panel, for storing the display data, said display memory; and

a digital/analog converter circuit provided on said display panel, for converting display data, represented by a digital signal read out of said display memory and transferred thereto, to an analog signal;

wherein said digital/analog converter circuit and said display memory are formed by a fabrication process identical with that for forming thin-film transistors of pixel switches in the display area.

5. A display device comprising:

a display panel having a display area in which a plurality of pixels are arrayed in the form of matrix at cross points of a plurality of data lines and a plurality of scanning lines;

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines; and

a data-line driver circuit for receiving display data supplied by a host device, and for applying signals corresponding to the display data to the plurality of data lines;

said display panel including;

at least,

a display memory, for storing the display data, said display memory; and

a voltage-to-current converting circuit for converting display data represented by a digital signal transferred from said display memory, to an analog current signal.

15. A display device comprising:

a display device substrate provided with a display area in which a plurality of pixels are arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit including;

a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits;

an output buffer for reading data out of said display memory and for outputting the data to said display device substrate; and

a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device,

(N×

B)/S-number of said output buffers being disposed in said controller unit, where (N×

B) bits correspond to one line of bits in the (M×

N×

B)-number of bits of said display memory and S represents a block dividing number,

one line of display data being transferred from said output buffers of said controller unit to said display device substrate via a data bus, said data bus having a width of (N×

B)/S bits, upon being divided S times, in one horizontal scanning period in units of (N×

B)/S bits;

said display device substrate including;

a data-line driver circuit; and

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines,

said data-line driver circuit including;

(N×

B)/S-number of level shifters, each level-shifting an amplitude of a signal received from the data bus to a signal having a higher amplitude;

(N×

B)/S-number of latch circuits, each latching an output signal of said level shifter;

(N/S)-number of digital/analog converter circuits, each receiving B-bit signals output from B-number of said latch circuits, for outputting an analog signal; and

a selector circuit to which the output of said digital/analog converter circuit is supplied and having N-number of outputs, which is the same as the N-number of columns of the display area, said selector circuit receiving outputs of (N/S)-number of said digital/analog converter circuits and, on the basis of a selector control signal, supplying data signals to group of S-number of the data lines sequentially, for each output of (N/S)-number of said digital/analog converter circuits, in a time obtained by dividing one horizontal scanning period by the block dividing number S.

16. The display device according to claim 15, wherein

said controller of said controller unit supplies a clock signal to a level shifter/timing buffer of said display device substrate;

and

a latch clock signal and the selector control signal boosted and output by the level shifter/timing buffer are supplied to said latch circuits and said selector, respectively.

21. The device according to claim 15, wherein a voltage/current converting circuit for converting the output voltage of said digital/analog converter circuit to a current, and a current output buffer for outputting a current, which is the result of the conversion by said voltage/current converting circuit, to said selector circuit, are provided between said digital/analog converter circuit and said selector circuit;

current being supplied from N outputs of said selector circuit to N data lines.

22. The device according to claim 15, wherein

said digital/analog converter circuit is replaced by a voltage/current converting circuit for converting display data represented by a digital signal transferred from said controller IC, to an analog current signal and currents output from N-number of outputs of said selector circuit are supplied to N-number of said data lines.

56. The device according to claim 15, wherein transistors, composing said display unit, said data-line driver circuit and said scanning-line driver circuit, have the same structure as regard to gate insulating film, the film thickness of gate insulating films of the transistors being equal within variances dependent on a fabrication process.

57. The device according to claim 15, wherein transistors formed on said display device substrate and constructing a peripheral circuit that includes said data-line driver circuit and scanning-line driver circuit are formed by a process identical with that for forming transistors that construct pixel switches of the display area formed on said display device substrate;

and

film thickness of gate insulating films of the transistors constructing the peripheral circuit that includes said data-line driver circuit and said scanning-line driver circuit are made the same as film thickness of gate insulating films of the transistors that construct said pixel switches.

80. The device according to claim 56, wherein said transistors comprise polysilicon thin-film transistors.

17. A display device comprising:

a display device substrate provided with a display area in which a plurality of pixels are arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit including a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits, an output buffer for reading data out of said display memory and for outputting the data to said display device substrate, and a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)/S-number of said output buffers being disposed in said controller unit, where (N×

B) bits correspond to one line of bits in the (M×

N×

B)-number of bits of said display memory and S represents a block dividing number;

one line of display data being transferred from said output buffers of said controller unit to said display device substrate via a data bus having a width of (N×

B)/S bits, upon being divided S times, in one horizontal scanning period in units of [(N×

B)/S] bits;

said display device substrate including;

a data-line driver circuit; and

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines,

said data-line driver circuit including;

(N×

B)/S-number of latch circuits, each latching a signal received from the data bus;

(N×

B)/S-number of level shifters, each level-shifting an amplitude of an output signal from said latch circuit to a signal having a higher amplitude;

(N/S)-number of digital/analog converter circuits, each receiving B-bit outputs from B-number of said level shifters, for outputting an analog signal; and

a selector circuit to which the output of said digital/analog converter circuit is supplied and having N-number of outputs being the same as the N-number of columns of the display area, said selector circuit receiving outputs of (N/S)-number of said digital/analog converter circuits and, on the basis of a selector control signal, supplying data signals to a group of S-number of the data lines sequentially, for every output from each digital/analog converter circuit, in a time obtained by dividing one horizontal scanning period by the block dividing number S.

18. The display device according to claim 17, wherein

said controller of said controller unit supplies a clock signal to a level shifter/timing buffer of said display device substrate;

and

a latch clock signal and the selector control signal boosted and output by the level shifter/timing buffer are supplied to said latch circuits and said selector, respectively.

20. The display device according to claim 17, wherein

said controller of said controller unit supplies a clock signal to a timing buffer of said display device substrate, and

a latch clock signal and the selector control signal from the timing buffer are supplied to said latch circuit and said selector circuit, respectively.

76. The device according to claim 17, wherein said digital/analog converter circuit is replaced by a voltage/current converting circuit for converting display data represented by a digital signal transferred from said controller IC, to an analog current signal and currents output from N-number of outputs of said selector circuit are supplied to N-number of said data lines.

19. A display device comprising:

a display device substrate provided with a display area in which a plurality of pixels arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit having a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits, an output buffer for reading data out of said display memory and outputting this data to said display device substrate, and a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)/S-number of said output buffers being disposed in said controller unit, where (N×

B) bits correspond to one row of bits in the (M×

N×

B)-number of bits of said display memory and S represents a block dividing number;

one line of display data being transferred from said output buffers of said controller unit to said display device substrate via a data bus having a width of (N×

B)/S bits, upon being divided S times, in one horizontal scanning period in units of (N×

B)/S bits;

said display device substrate including;

a data-line driver circuit and

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines,

said data-line driver circuit including;

(N×

B)/S-number of latch circuits, each latching a signal received from the data bus;

(N/S)-number of digital/analog converter circuits, each receiving B-bit outputs from B-number of said latch circuits, for outputting an analog signal; and

a selector to which the output of said digital/analog converter circuit is supplied and having N-number of outputs being the same as the N-number of columns of the display area, said selector circuit receiving outputs of (N/S)-number of said digital/analog converter circuits and, on the basis of a selector control signal, supplying data signals to a group of S-number of the data lines sequentially, for every output from each digital/analog converter circuit, in a time obtained by dividing one horizontal scanning period by the block dividing number S.

77. The device according to claim 19, wherein said digital/analog converter circuit is replaced by a voltage/current converting circuit for converting display data represented by a digital signal transferred from said controller IC, to an analog current signal and currents output from N-number of outputs of said selector circuit are supplied to N-number of said data lines.

23. A display device comprising:

a display device substrate provided with a display area in which a plurality of pixels are arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit having a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits, an output buffer for reading data out of said display memory and for outputting this data to said display device substrate, and a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)/S-number of said output buffers being disposed in said controller unit, where (N×

B) bits correspond to one line of bits in the (M×

N×

B)-number of bits of said display memory and S represents a block dividing number;

one line of display data being transferred from said output buffers of said controller unit to said display device substrate via a data bus, which has a width of (N×

B)/S bits, upon being divided S times in one horizontal scanning period, in units of (N×

B)/S bits;

said display device substrate including;

a data-line driver circuit and

scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines,

said data-line driver circuit including;

(N×

B)/S-number of level shifters, each level-shifting an amplitude of a signal received from the data bus to a signal having a higher amplitude;

(N×

B)/S-number of latch circuits, each latching an output of said level shifter;

(N/S)-number of decoder circuits, each receiving B-bit outputs from B-number of said latch circuits;

(N/S)-number of current output buffers, each receiving an output of said decoder circuit, for outputting a current conforming to a result of decoding;

a selector circuit to which the output current of said current output buffer is supplied and having N-number of outputs, which is the same as the N-number of columns of the display area, said selector circuit receiving current outputs of said (N/S)-number of current output buffer circuits and, on the basis of a selector control signal, and supplying current output to a group of S-number of the data lines sequentially, on a per-output basis, in a time obtained by division by the block dividing number S.

24. The device according to claim 23, wherein

said controller of said controller unit supplies a clock signal to a level shifter/timing buffer of said display device substrate;

and

a latch clock signal and the selector control signal boosted by the level shifter/timing buffer, are supplied to said latch circuits and said selector, respectively.

25. A display device comprising:

a display device substrate provided with a display area in which a plurality of pixels are arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit having a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits, an output buffer for reading data out of said display memory and outputting the data to said display device substrate, and a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)-number of said output buffers being disposed in said controller unit, where (N×

B) corresponds to one row of bits in the (M×

N×

B)-number of bits of said display memory;

one line of display data being transferred in parallel by a single transfer from said output buffers of said controller unit to said display device substrate via a data bus having a width of (N×

B) bits;

said display device substrate including;

a data-line driver circuit; and

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines,

said data-line driver circuit including;

(N×

B)-number of level shifters, each level-shifting an amplitude of a signal received from the data bus to a signal having a higher amplitude;

(N×

B)-number of latch circuits, each latching an output of said level shifter; and

N-number of digital/analog converter circuits, each receiving B-bit outputs from B-number of said latch circuits, for outputting an analog signal.

26. The device according to claim 25, wherein

said controller of said controller unit supplies a clock signal to a level shifter/timing buffer of said display device substrate;

and

a latch clock signal, boosted by the level shifter/timing buffer, is supplied to said latch circuits.

27. A display device comprising:

a display device substrate provided with a display area in which a plurality pixels are arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit including a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits, an output buffer for reading data out of said display memory and outputting this data to said display device substrate, and a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)-number of said output buffers being disposed in said controller unit, where (N×

B) corresponds to one row of bits in the (M×

N×

B)-number of bits of said display memory;

one line of display data being transferred in parallel by a single transfer from said output buffers of said controller unit to said display device substrate via a data bus having a width of (N×

B) bits;

said display device substrate including;

a data-line driver circuit; and

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines,

said data-line driver circuit including;

(N×

B)-number of latch circuits, each latching a low-amplitude signal received from the data bus;

(N×

B)-number of level shifter for level-shifting an amplitude of an output signal of said latch circuit to a signal having a higher amplitude; and

N-number of digital/analog converter circuits, each receiving B-bit outputs from B-number of said level shifters, for outputting an analog signal.

28. The device according to claim 27, wherein

said controller of said controller unit supplies a clock signal to a level shifter/timing buffer of said display device substrate;

and

a latch clock signal, boosted by the level shifter/timing buffer, is supplied to said latch circuits.

29. A display device comprising:

a display device substrate provided with a display area in which a plurality of pixels are arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit having a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits, an output buffer for reading data out of said display memory and outputting the data to said display device substrate, and a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)-number of said output buffers being disposed in said controller unit, where (N×

B) corresponds to one row of bits in the (M×

N×

B)-number of bits of said display memory;

one line of display data being transferred from said output buffers of said controller unit to said display device substrate via a data bus, which has a width of (N×

B) bits, in one horizontal scanning period;

said display device substrate including;

a data-line driver circuit; and

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines,

said data-line driver circuit including;

(N×

B)-number of latch circuits, each latching a signal received from the data bus; and

N-number of digital/analog converter circuits, each receiving B-bit outputs from B-number of said latch shifters, for outputting an analog signal.

30. The device according to claim 29, wherein

said controller of said controller unit supplies a clock signal to a timing buffer of said display device substrate;

and

a latch clock signal from the timing buffer is supplied to said latch circuits.

31. A display device comprising:

a display device substrate provided with a display area in which a plurality of pixels are arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit having a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits, an output buffer for reading data out of said display memory and outputting the data to said display device substrate, and a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)-number of said output buffers being disposed in said controller unit, where (N×

B) corresponds to one row of bits in the (M×

N×

B)-number of bits of said display memory;

one line of display data being transferred in parallel by a single transfer from said output buffers of said controller unit to said display device substrate via a data bus having a width of (N×

B) bits;

said display device substrate including;

a data-line driver circuit; and

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines,

said data-line driver circuit comprising;

(N×

B)-number of level shifters, each level-shifting an amplitude of a signal received from the data bus to a signal having a higher amplitude;

(N×

B)-number of latch circuits, each latching an output of said level shifter; and

N-number of digital/analog converter circuits, each receiving B-bit outputs from B-number of said latch circuit, for outputting an analog signal; and

N-number of voltage/current converting circuit/current output buffer circuit, each receiving an output of said digital/analog converting circuit, for outputting current to corresponding data line.

32. The device according to claim 31, wherein

said controller of said controller unit supplying a clock signal to a level shifter/timing buffer of said display device substrate;

and

a latch clock signal from the level shifter/timing buffer being supplied to said latch circuits.

33. The device according to claim 31, wherein said digital/analog converter circuit and said voltage/current converting circuit/current output buffer circuit are replaced by a voltage/current converting circuit, to which a B-bit output of said latch circuit is supplied, for converting said B-bit outputs to an analog current signal.

34. The device according to claim 31, wherein said digital/analog converter circuit and said voltage/current converting circuit/current output buffer circuit are replaced by a decoder circuit, to which a B-bit output of said latch circuit is supplied, for decoding the output;

and

said display device substrate further includes a current output buffer circuit, to which an output of said decoder circuit is supplied, for outputting current conforming to corresponding data line.

35. A display device comprising:

a display device substrate provided with a display area in which a plurality of pixels are arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit having a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits, an output buffer for reading data out of said display memory and outputting this data to said display device substrate, and a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)/(P×

S)-number of said output buffers being disposed in said controller unit, where (N×

B) bits correspond to one row of bits in the (M×

N×

B)-number of bits of said display memory, S represents a block dividing number and P represents number of phases;

display data being transferred from said output buffers of said controller unit to said display device substrate via a data bus, which has a width of (N×

B)/(P×

S) bits, with one line of display data being transferred, upon dividing (N×

B)/(P×

S)-bit data (P×

S) times, in one horizontal scanning period,

said display device substrate including;

a data-line driver circuit having;

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines.

said data-line driver circuit comprising;

(N×

B)/(P×

S)-number of level shifters, each level-shifting am amplitude of a signal received from the data bus to a signal having a higher amplitude;

(N×

B)/(P×

S)-number of serial/parallel converter circuits, each receiving an output from said level shifter serially, for expanding the output into P-phase parallel bits and outputting the parallel bits;

(N×

B)/S-number of latch circuits, each latching the output of said serial/parallel converter circuit;

(N/S)-number of digital/analog converter circuits, receiving B-bit outputs from B-number of said latch circuit, for outputting an analog signal; and

a selector circuit to which the output of said digital/analog converter circuit is supplied and having N-number of outputs, which is the same as the N-number of columns of the display area, said selector circuit receiving outputs of (N/S)-number of said digital/analog converter circuits and, on the basis of a selector control signal, supplying data signals to a group of S-number of the data lines sequentially, for every output from each digital/analog converter circuit, in a time obtained by division by the block dividing number S.

36. The device according to claim 35, wherein

said controller of said controller unit supplies a clock signal to a level shifter/timing buffer of said display device substrate;

and

a latch clock signal, the selector control signal and a serial/parallel conversion control signal, boosted by the level shifter/timing buffer, are supplied to said latch circuits, said selector and said serial/parallel converter circuit, respectively.

41. The device according to claim 35, wherein a voltage/current converting circuit &

current output buffer circuit for subjecting an output of said digital/analog converter circuit to voltage-to-current conversion and outputting current is provided between the digital/analog converter circuit and said selector.

42. The device according to claims 35, wherein said digital/analog converter circuit is replaced by a voltage/current converting circuit for receiving the outputs of said latch circuits and for converting said the outputs to an analog current signal.

43. The device according to claim 35, wherein (N/S)-number of decoder circuits, to which outputs from respective ones of B-number of said latch circuits are input, for decoding these outputs, and (N/S)-number of current output buffers for outputting current corresponding to results of decoding by said decoder circuits, are provided instead of said digital/analog converter circuit between said latch circuits and said selector.

37. A display device comprising:

a display device substrate provided with a display area in which a plurality of pixels are arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit having a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits, an output buffer for reading data out of said display memory and outputting this data to said display device substrate, and a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)/(P×

S)-number of said output buffers being disposed in said controller unit, where (N×

B) bits correspond to one row of bits in the (M×

N×

B)-number of bits of said display memory, S represents a block dividing number and P represents number of phases;

display data being transferred from said output buffers of said controller unit to said display device substrate via a data bus, which has a width of (N×

B)/(P×

S) bits, with one line of display data being transferred, upon dividing (N×

B)/(P×

S)-bit data (P×

S), times in one horizontal scanning period,

said display device substrate including;

a data-line driver circuit having;

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines.

said data-line driver circuit comprising;

(N×

B)/(P×

S) number of serial/parallel converter circuits, each receiving bit data transferred to the data bus serially, for expanding the data into P-phase parallel bits;

(N×

B)/(P×

S)-number of latch circuits, each latching the output of said serial/parallel converter circuit;

(N×

B)/S-number of level shifters, each level-shifting an output of said latch circuit;

(N/S)-number of digital/analog converter circuits, each receiving B-bit outputs from B-number of said level shifters, for outputting an analog signal; and

a selector circuit to which the output of said digital/analog converter circuit is supplied and having N-number of outputs, which is the same as the N-number of columns of the display area, said selector circuit receiving outputs of (N/S)-number of said digital/analog converter circuits and, on the basis of a selector control signal, supplying data signals to group of S-number of the data lines sequentially, for every output from the digital/analog converter circuits, in a time obtained by division by the block dividing number S.

38. The device according to claim 37, wherein

said controller of said controller unit supplies a clock signal to a level shifter/timing buffer of said display device substrate;

and

a latch clock signal, the selector control signal and a serial/parallel conversion control signal, boosted by the level shifter/timing buffer, are supplied to said latch circuits, said selector and said serial/parallel converter circuit, respectively.

78. The device according to claim 37, wherein said digital/analog converter circuit is replaced by a voltage/current converting circuit for receiving the outputs of said latch circuits and for converting said the outputs to an analog current signal.

39. A display device comprising:

a display device substrate provided with a display area in which a plurality of pixels are arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit having a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits, an output buffer for reading data out of said display memory and outputting this data to said display device substrate, and a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)/(P×

S)-number of said output buffers being disposed in said controller unit, where (N×

B) bits correspond to one row of bits in the (M×

N×

B)-number of bits of said display memory, S represents a block dividing number and P represents number of phases;

display data being transferred from said output buffers of said controller unit to said display device substrate via a data bus, which has a width of (N×

B)/(P×

S) bits, with one line of display data being transferred, upon dividing [(N×

B)/(P×

S)]-bit data (P×

S) times, in one horizontal scanning period;

said display device substrate including;

a data-line driver circuit; and

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines;

said data-line driver circuit comprising;

(N×

B)/S-number of serial/parallel converter circuits, each receiving bit data from the data bus serially, for expanding the serial data into P-phase parallel bits;

(N×

B)/S-number of latch circuits, each latching the output of said serial/parallel converter circuit;

(N/S)-number of digital/analog converter circuits, each receiving B-bit outputs from B-number of said latch circuits, for outputting an analog signal; and

a selector circuit to which the output of said digital/analog converter circuit is supplied and having N-number of outputs, which is the same as the N-number of columns of the display area;

said selector circuit receiving outputs of (N/S)-number of said digital/analog converter circuits and, on the basis of a selector control signal, supplying data signals to a group of S-number of the data lines sequentially, for every output from each digital/analog converter circuit, in a time obtained by division by the block dividing number S.

40. The device according to claim 39, wherein

said controller of said controller unit supplies a clock signal to a timing buffer of said display device substrate;

and

a latch clock signal, the selector control signal and a serial/parallel conversion control signal from the timing buffer are supplied to said latch circuits, said selector and said serial/parallel converter circuit, respectively.

79. The device according to claim 39, wherein said digital/analog converter circuit is replaced by a voltage/current converting circuit for receiving the outputs of said latch circuits and for converting said the outputs to an analog current signal.

44. A display device comprising:

a display device substrate provided with a display area in which a plurality of pixels are arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit having a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits, an output buffer for reading data out of said display memory and for outputting the data to said display device substrate, and a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)/P-number of said output buffers being disposed in said controller unit;

one line of display data being transferred from said output buffers of said controller unit to said display device substrate via a data bus, which has a width of (N×

B)/P bits, upon being divided P times per horizontal scanning period,

said display device substrate including;

data-line driver circuit; and

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines,

said data-line driver circuit comprising;

(N×

B)/P-number of level shifters, each level-shifting an amplitude of a signal received from the data bus to a signal having a higher amplitude;

(N×

B)/P-number of serial/parallel converter circuits, each receiving an output from said level shifter serially, for expanding the output into P-phase parallel bits;

(N×

B)-number of latch circuits, each latching the output of said serial/parallel converter circuit; and

N-number of digital/analog converter circuits, each receiving B-bit outputs from B-number of said latch circuits, for outputting an analog signal.

45. The device according to claim 44, wherein

said controller of said controller unit supplies a clock signal to a level shifter/timing buffer of said display device substrate;

and

a latch clock signal and a serial/parallel conversion control signal, boosted by the level shifter/timing buffer, are supplied to said latch circuits and said serial/parallel converter circuit, respectively.

46. The device according to claim 44, wherein, on said display device substrate, positions of said level shifter and said serial/parallel converter circuit are interchanged;

said serial/parallel converter circuit, to which each bit signal of the data bus is serially supplied, expands the serial bit signal into P-phase parallel bits;

said level shifter level-shifts the amplitude of an output signal of said serial/parallel converter circuit to a signal having a higher amplitude; and

said digital/analog converter circuit has the outputs of said latch circuits supplied thereto.

47. A display device comprising:

a display device substrate provided with a display area in which a plurality of pixels are arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit having a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits, an output buffer for reading data out of said display memory and outputting this data to said display device substrate, and a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)/P-number of said output buffers being disposed in said controller unit, where (N×

B)/P corresponds to a number obtained by dividing one row of bits in the (M×

N×

B)-number of bits of said display memory by P phases;

one line of display data being transferred from said output buffers of said controller unit to said display device substrate via a data bus, which has a width of (N×

B)/P bits, upon being divided P times per horizontal scanning period,

said display device substrate including;

data-line driver circuit; and

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines,

said data-line driver circuit comprising;

(N×

B)/P-number of serial/parallel converter circuits, each receiving data from the data bus serially, for expanding the data into P-number of parallel bits;

(N×

B)-number of latch circuits, each latching the output of said serial/parallel converter circuit; and

N-number of digital/analog converter circuits, each receiving B-bit outputs from B-number of said latch circuits, for outputting an analog signal.

48. The device according to claim 47, wherein

said controller of said controller unit supplies a clock signal to a timing buffer of said display device substrate;

and

a latch clock signal and a serial/parallel conversion control signal from the timing buffer, are supplied to said latch circuits and said serial/parallel converter circuit, respectively.

49. The device according to claim 47, further comprising N-number of voltage/current converting circuits &

current output buffer circuits, to which an output voltage from said digital/analog converter circuit is supplied, for applying a voltage-to-current conversion and outputting current.

50. The device according to claim 47, wherein said digital/analog converter circuit is replaced by a voltage/current converting circuit for receiving the outputs of said latch circuits and for converting said the outputs to an analog current signal.

51. The device according to claim 47, wherein said digital/analog converter circuits are replaced by N-number of decoder circuits, to which outputs from B-number of said latch circuits are input, for decoding these outputs, and N-number of current output buffer circuits for outputting current conforming to results of decoding by said decoder circuits.

52. A display device having a display device substrate including:

a display area having pixels arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines;

a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits;

an output buffer for reading data out of said display memory and outputting this data to said display device substrate; and

a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)/(P×

S)-number of said output buffers being provided, where (N×

B) bits correspond to one row of bits in the (M×

N ×

B)-number of bits of said display memory, S represents a block dividing number and P represents number of phases;

said display device substrate including;

data-line driver circuit; and

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines,

said data-line driver circuit comprising;

(N×

B)/(P×

S)-number of serial/parallel converter circuits, each receiving the output of said output buffer serially, for expanding a serial bit data into P-phase parallel bits;

(N×

B)/S-number of latch circuits, each latching the output of said serial/parallel converter circuit;

(N/S)-number of digital/analog converter circuits, each receiving B-bit outputs from B-number of said latch circuits, for outputting an analog signal; and

a selector circuit to which the output of said digital/analog converter circuit is supplied and having N-number of outputs, which is the same as the N-number of columns of the display area, said selector circuit receiving outputs of (N/S)-number of said digital/analog converter circuits and, on the basis of a selector control signal, supplying data signals to group of S-number of the data lines sequentially, for every output from each digital/analog converter circuit, in a time obtained by division by the block dividing number S.

53. The device according to claim 52, wherein

said controller supplying a latch clock signal to said latch circuits, supplies the selector control signal to said selector circuits, and a serial/parallel conversion control signal to said serial/parallel converter circuits.

54. A display device having a display device substrate including:

a display area having a plurality pixels arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines;

a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits;

an output buffer for reading data out of said display memory and for outputting the data to said display device substrate; and

a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

(N×

B)/P-number of said output buffers being provided, where (N×

B) bits correspond to one row of bits in the (M×

N×

B)-number of bits of said display memory, and P represents number of phases;

said display device substrate including;

data-line driver circuit; and

a scanning-line driver circuit for applying voltage sequentially to the plurality of scanning lines,

said data-line driver circuit comprising;

(N×

B)/P-number of serial/parallel converter circuits, each receiving the output of said output buffer serially, for expanding serial data into P-phase parallel bits;

(N×

B)-number of latch circuits, each latching the output of said serial/parallel converter circuit; and

N-number of digital/analog converter circuits, receiving B-bit outputs from B-number of said latch circuits, for outputting an analog signal.

55. The device according to claim 54, wherein

said controller supplies a latch clock signal to said latch circuits and supplies a serial/parallel conversion control signal to said serial/parallel converter circuits.

58. A display device including a data-line driver circuit that has at least a digital/analog converter circuit for converting, to an analog signal, one line of a digital signal, or one line of a digital signal that has been divided into a plurality of portions, transferred in parallel thereto upon being read out of a display memory circuit storing display data, said data-line driver applying analog data to a plurality of data lines of a display area;

said digital/analog converter circuit, or said digital/analog converter circuit and said display memory circuit, being formed on the same substrate as that of the display area;

gate insulating films of transistors that construct circuits formed on the same substrate as that of said display area being identical in film thickness with gate insulating films of transistors that construct pixel switches of the display area, and film thickness of gate insulating films of the transistors being made the same within variances of a fabrication process.

81. The device according to claim 58, wherein said transistors comprise polysilicon thin-film transistors

60. A display device having a data-line driver circuit, which receives display data supplied by a host device, for applying signals corresponding to display data to data lines, wherein at least wiring for transferring a display signal does not intersect wiring for displaying another display signal in a circuit for subjecting display data to a phase expansion.

61. A semiconductor device having a data-line driver circuit, which receives data supplied by a host device, for applying signals corresponding to data to data lines, wherein at least wiring for transferring a data signal does not intersect wiring for displaying another data signal in a circuit for subjecting data to a phase expansion.

62. A display device having a circuit, which receives display data supplied by a host device, for subjecting display data to a phase expansion;

wherein a number C of intersection points at which a certain signal line that transmits a signal prior to phase expansion intersects other signal lines is less than

C=n(n−

1)(k−

1)/2

where n represents degree to which supplied display data is parallel, and k×

n represents degree to which display data is parallel after phase expansion.

63. A semiconductor device having a circuit, which receives data supplied by a host device, for subjecting said data to a phase expansion;

wherein a number C of intersection points at which a certain de-ta signal line that transmits a data signal prior to phase expansion intersects other data signal lines is less than

C=n(n−

1)(k−

1)/2

where n represents degree to which supplied data is parallel, and k×

n represents degree to which data is parallel after phase expansion.

64. A display device comprising:

a display device substrate provided with a display area in which a plurality pixels are arrayed in M rows and N columns in the form of a matrix at cross points of a plurality (N) of data lines and a plurality (M) of scanning lines; and

a controller unit having a display memory for storing (M×

N) pixels of B-bit grayscale display data, for a total of (M×

N×

B) bits, an output buffer for reading data out of said display memory and outputting this data to said display device substrate, and a controller for controlling said display memory and said output buffer as well as managing communication and control with a host device;

digital display data being transferred from the output buffer of said controller unit to said display device substrate via a data bus having a bit width of (N×

B)/(P×

S) bits obtained by dividing (N×

B) bits, which correspond to one row of bits in the (M×

N×

B)-number of bits of said display memory, by the product of a block dividing number S and P-number of phases;

said display device substrate including a data-line driver circuit for driving data lines of the display area,

said data-line driver circuit comprising;

(N×

B)/(P×

S) number of P-phase expansion circuits, each including;

P-number of level shift circuits, connected in common with one data line of the data bus, for level-shifting the amplitudes of P-phase signals output from said output buffer and received sequentially via the data line to respective ones of signals having a higher amplitude; and

latch circuits for latching respective ones of outputs of said P-number of lever shifter circuits in accordance with a driving clock, expanding P-phase serial bit data into level-shifted P-bit parallel data, and latching and outputting this data;

(N×

B)/S-bit data being output in parallel from (N×

B)/(P×

S)-number of said P-phase expansion circuits provided in correspondence with the data bus having the bit width of (N×

B)/(P×

S) bits;

(N/S)-number of said digital/analog converter circuits, provided for (N×

B)/(P×

S)-number of said P-phase expansion circuits, each of said digital/analog converter circuits receiving B-bit data from said P-phase expansion circuits, for outputting an analog signal; and

a selector circuit, receiving outputs of (N/S)-number of said digital/analog converter circuits as inputs and having N-number of outputs connected to N-number of data lines of the display area, for supplying outputs of (N/S)-number of said digital/analog converter circuits to a group of data lines of the display area sequentially in a time obtained by division by the block dividing number S.

65. The device according to claim 64, wherein one line of display data obtained by dividing (N×

B)/(P×

S)-bit digital video data (P×

S) times is transferred from said controller unit to the data-line driver circuit of said display device substrate in one horizontal scanning period.

66. The device according to claim 64, wherein said P-phase expansion circuit includes as said level shift circuits:

first to third switch elements connected serially between a high-voltage power source and a low-voltage power-supply;

a first capacitor connected to a connection point between said first and second switch elements;

a fourth switch element connected between an input terminal, to which an input signal is supplied, and a control terminal of said third switch element; and

a second capacitor connected to a connection point between the control terminal of said third switch element and said fourth switch element;

wherein a first sampling control signal is supplied to both a control terminal of said first switch element and a control terminal of said second switch element, whereby one of these switch elements is turned off when the other is turned on;

a second sampling control signal is supplied to a control terminal of said fourth switch; and

terminal voltage of said first capacitor is extracted as an output signal directly or indirectly.

67. The device according to claim 64, wherein said P-phase expansion circuit includes as said level shift circuits:

first to third switch elements connected serially between a high-voltage power source and a low-voltage power-supply;

a first capacitor connected to a connection point between said first and second switch elements;

a fourth switch element connected between an input terminal, to which an input signal is supplied, and a control terminal of said third switch element; and

a second capacitor connected to a connection point between the control terminal of said third switch element and said fourth switch element;

wherein a first sampling control signal is supplied to both a control terminal of said first switch element and a control terminal of said second switch element;

said first switch element is turned on, said second switch element is turned off and said first capacitor is charged to the voltage of the high-voltage power-supply when the first sampling control signal is a second logic value;

a second sampling control signal is supplied to a control terminal of said fourth switch element;

said fourth switch element is turned on and said second capacitor is charged by the input signal voltage when the second sampling control signal is a first logic value;

said first switch element is turned off and said second switch element is turned on when the first sampling control signal is the first logic value; and

terminal voltage of said first capacitor prevailing at this time is extracted as an output signal directly or indirectly.

68. The device according to claim 64, wherein said P-phase expansion circuit comprises a 2-phase expansion circuit, said 2-phase expansion circuit comprising:

first and second level shift circuits having input terminals thereof connected in common with a data line;

said first level shift circuit including;

first to third switch elements connected serially between a high-voltage power-supply and a low-voltage power-supply;

a first capacitor connected to a connection point between said first and second switch elements;

a fourth switch element connected between an input terminal, to which an input signal is supplied, and a control terminal of said third switch element; and

a second capacitor connected to a connection point between the control terminal of said third switch element and said fourth switch element;

wherein a first sampling control signal is supplied to both a control terminal of said first switch element and a control terminal of said second switch element;

said first switch element is turned on, said second switch element is turned off and said first capacitor is charged to the voltage of the high-voltage power-supply when the first sampling control signal is a second logic value;

a second sampling control signal, which is the complement of the first sampling control signal, is supplied to a control terminal of said fourth switch element;

said fourth switch element is turned on and said second capacitor is charged by the input signal voltage when the second sampling control signal is a first logic value;

said first switch element is turned off and said second switch element is turned on when the first sampling control signal is the first logic value; and

terminal voltage of said first capacitor prevailing at this time is extracted as an output signal directly or indirectly;

said second level shift circuit having a circuit structure identical with that of said first level shift circuit;

an input signal being applied commonly to both of said first and second sampling level converting circuits; and

the second sampling control signal being input commonly to the control terminal of said first switch element and the control terminal of said second switch element of said second level shift circuit, and the first sampling control signal being input to the control terminal of said fourth switch element of said second level shift circuit;

a first master/slave latch, in which an output signal of said first level shift circuit is loaded based upon the first sampling control signal, for outputting this signal based upon the second sampling control signal;

a latch for delivering the output signal of said first master/slave latch based upon the first sampling control signal; and

a second master/slave latch, in which an output signal of said second level shift circuit is loaded based upon the second sampling control signal, for outputting this signal based upon the first sampling control signal.

69. A semiconductor device comprising:

an array unit in which a plurality of devices to be driven are arrayed in a form of a matrix; and

a serial/parallel converting circuit unit having more than 1 bit input for performing parallel processing of data for driving said device to be driven,

said serial/parallel converting circuit unit comprised of a plurality of serial/parallel converting circuits, each having one bit input.

70. The semiconductor device according to claim 69, wherein at least two number of serial/parallel converting circuits among said serial/parallel converting circuits are driven synchronously by a control line connected in common to said two number of serial/parallel converting circuits.

71. A semiconductor device comprising:

an array unit in which a plurality of devices to be driven are arrayed in a form of a matrix;

a driver circuit for writing an electric signal into said devices to be driven; and

a serial/parallel converting circuit unit having more than 1 bit input for performing parallel processing of data,

a group of output nodes for outputting a signal obtained on serial/parallel converting data supplied to a first input node of said serial/parallel converting circuit unit, and a group of output nodes for outputting a signal obtained on serial/parallel converting data supplied to a second input node, adjacent to said first input node of said serial/parallel converting circuit unit being arranged adjacent.

72. A semiconductor device comprising:

an array unit in which a plurality of devices to be driven are arrayed in the form of a matrix;

a driver circuit for writing an electric signal into said devices to be driven; and

a serial/parallel converting circuit unit having more than 1 bit input for performing parallel processing of data,

said serial/parallel converting circuit unit being arranged with a layout pattern having substantially a form of a rectangle, a group of input nodes of said serial/parallel converting circuit unit being provided on one of longer sides of said rectangle and a group of output nodes of said serial/parallel converting circuit unit being provided on another longer side f said rectangle.