Nonvolatile semiconductor memory device and method of detecting overerased cell

• US 20030067818A1
• Filed: 09/12/2002
• Published: 04/10/2003
• Est. Priority Date: 09/12/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Hirano, Yasuaki
• Granted Patent: US 6,714,459 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step

Abstract

In a nonvolatile semiconductor memory device, overerase-verify in an erase operation is conducted in units of bit lines in a batch. A cell current of a reference cell and voltage applied to a word line of a main cell are set so as to have a detection level at which there can be one or no memory cell having a threshold voltage of 0.5 V at time of one overerase-verify operation and a leak current of an unselected memory cell can be 1 μ A or lower in a normal operation. Thus, the number of verify times in the overerase-verify is reduced to shorten period of time in the overerase-verify and thereby achieve high-speed erase. Furthermore, a cell current can be reduced to achieve lower power consumption.

Claims

1. A nonvolatile semiconductor memory device comprising:

a memory cell array including;

a plurality of floating gate electric field effect transistors arranged in a matrix, each having a control gate, a drain and a source and being capable of electrically writing and erasing information, wherein a threshold voltage of each of the floating gate electric field effect transistors in a written state is higher than a threshold voltage of each of the floating gate electric field effect transistors in an erased state,

a plurality of row lines connected to control gates of the floating gate electric field effect transistors arranged in a row direction,

a plurality of column lines connected to drains of the floating gate electric field effect transistors arranged in a column direction, and

a common line commonly connected to sources of the floating gate electric field effect transistors constituting a block; and

a erase processing means which performs erase processing where, by controlling voltages applied to the row lines, the column lines and the common wiring,

firstly write before erase is performed,

secondly write-verify before erase is performed,

thirdly an erase pulse is applied,

fourthly verify after erase pulse application is performed,

fifthly first verify is performed to detect an overerased cell,

sixthly, when an overerased cell is detected in the first verify by applying a voltage to one of the row lines, second verify is performed to specify the overerased cell by applying a voltage different from the voltage applied in the first verify to the row line, and

seventhly, when the overerased cell is specified as a result of the second verify, write of a software program is performed for the overerased cell.

2. The nonvolatile semiconductor memory device according to claim 1, wherein

the erase processing means has the first verify means which performs the first verify in units of the column lines by applying a voltage to all row lines connected to control gates of the plurality of floating gate electric field effect transistors whose drains are commonly connected to the column line so that one floating gate electric field effect transistor in an overerased state at most exists among the plurality of floating gate electric field effect transistors, and that a leakage current when the floating gate electric field effect transistor in an overerased state is unselected in a normal operation can be equal to a predetermined value or lower.

3. A method of detecting an overerased cell in the nonvolatile semiconductor memory device according to claim 1, wherein

pass or failure is determined at time of the first verify and the second verify by comparing a current value of the column line connected to a drain of a reference cell and a current value of the column line connected to a drain of a target cell composed of a floating gate electric field effect transistor to be verified, the reference cell being composed of a floating gate electric field effect transistor which has the same structure as that of the aforementioned floating gate electric field effect transistor and is not written or erased.

4. The method of detecting an overerased cell in a nonvolatile semiconductor memory device according to claim 3, wherein

the first verify and the second verify are performed by using the same reference cell.

5. The method of detecting an overerased cell in a nonvolatile semiconductor memory device according to claim 3, wherein

a first voltage is lower than a second voltage, a third voltage is lower than a fourth voltage, and the first voltage is lower than the third voltage, where

a voltage applied to a row line connected to a control gate of the target cell at time of the first verify is defined as the first voltage,

a voltage applied to a row line connected to a control gate of the reference cell at time of first verify is defined as the second voltage,

a voltage applied to the row line connected to the control gate of the target cell at time of the second verify is defined as the third voltage, and

a voltage applied to the row line connected to the control gate of the reference cell at time of the second verify is defined as the fourth voltage.

6. The method of detecting an overerased cell in a nonvolatile semiconductor memory device according to claim 3, wherein

current values in the reference cell and the target cell are compared by a sense amplifier, and

at time of the first verify, a predetermined voltage for detecting an overerased cell is applied to all the row lines in the block, while the column lines are successively selected and connected to the sense amplifier to detect the overerased cell in units of the column lines.

7. The method of detecting an overerased cell in a nonvolatile semiconductor memory device according to claim 6, wherein

at time of the second verify, a voltage different from the voltage applied to the row lines at time of the first verify is successively applied to the row lines, and only a column line determined as including an overerased cell at time of the first verify is connected to the sense amplifier so as to specify the overerased cell in units of individual target cells.

8. The method of detecting an overerased cell in a nonvolatile semiconductor memory device according to claim 3, wherein

the floating gate electric field effect transistor having a threshold voltage between 0 and 1 V inclusive in the memory cell array is detected as the overerased cell at time of the first verify and the second verify.

9. A method of detecting an overerased cell in the nonvolatile semiconductor memory device according to claim 1, wherein

pass or failure at time of the first verify is determined based on a voltage value of the column line connected to the drain of a target cell composed of a floating gate electric field effect transistor to be verified, and

pass or failure at time of the second verify is determined by comparing a current value of the column line connected to the drain of a reference cell and a current value of the column line connected to the drain of the target cell, the reference cell being composed of a floating gate electric field effect transistor which has the same structure as that of the aforementioned floating gate electric field effect transistor and is not written or erased.

10. The method of detecting an overerased cell in a nonvolatile semiconductor memory device according to claim 9, wherein

a voltage between 0 and 1 V inclusive is applied to the row line connected to the control gate of the target cell at time of first verify.

11. The method of detecting an overerased cell in a nonvolatile semiconductor memory device according to claim 9, wherein

a voltage of a column line connected to the target cell is detected by a sense amplifier at time of the first verify, and

a leakage current to be detected is controlled by controlling time when the column line connected to the drain of the target cell is connected to the sense amplifier.

12. The method of detecting an overerased cell in a nonvolatile semiconductor memory device according to claim 9, wherein

a sixth voltage is lower than a seventh voltage, where

a voltage applied to a row line connected to the control gate of the target cell at time of the first verify is defined as a fifth voltage,

a voltage applied to the row line connected to the control gate of the target cell at time of second verify is defined as the sixth voltage, and

a voltage applied to a row line connected to the control gate of the reference cell at time of the second verify is defined as the seventh voltage.

13. The method of detecting an overerased cell in a nonvolatile semiconductor memory device according to claim 9, wherein

a voltage value of the column line connected to the target cell is detected by a first sense amplifier, and

at time of the first verify, a predetermined voltage for detecting an overerased cell is applied to all the row lines in the block, and the column lines are successively selected to be connected to the first sense amplifier so as to detect the overerased cell in units of the column lines.

14. The method of detecting an overerased cell in a nonvolatile semiconductor memory device according to claim 13, wherein

current values in the reference cell and the target cell are compared by a second sense amplifier at time of the second verify, and

at time of the second verify, a voltage different from the voltage applied to the row line at time of the first verify is successively applied at time of the second verify, and only column lines determined as including an overerased cell at time of the first verify are successively connected to the second sense amplifier so as to specify the overerased cells in units of individual target cells.