Packet preprocessing interface for multiprocessor network handler

• US 20030067930A1
• Filed: 10/05/2001
• Published: 04/10/2003
• Est. Priority Date: 10/05/2001
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Salapura, Valentina, Georgiou, Christos J.
• Granted Patent: US 6,904,040 B2
• Time in Patent Office: Days
• US Class Current: 370/412
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/125 by balancing the load, e.g. traffic engineering
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

A network handler uses a DMA device to assign packets to network processors in accordance with a mapping function which classifies packets based on its content, e.g., bits in one or more header fields. Preferably, the mapping function is implemented as a hash function, which uses a predetermined number of bits from packet as inputs. The result of this function specifies the processor to which the packet is assigned. To make implementation manageable in a high-traffic environment, each processor may be equipped with a queue, which holds pointer information. Such a pointer provides an indication of the area in memory where incoming packet resides. The network handler is particularly useful in a Fibre Channel environment, where the hash function may be implemented to assign all packets from the same sequence to the same processor, thereby resulting in improved processing efficiency.

Claims

1. A method for processing packets in a network, said network including a direct memory access (DMA) device including an input port, a memory unit, a plurality of processors, and an output port, said method comprising:

receiving a packet through the input port;

performing a mapping function which includes assigning said packet based on information contained in said packet; and

sending said packet to one of said plurality of processors based on the assignment performed by said mapping function.

2. The method of claim 1, wherein said mapping function assigns a plurality of packets in a manner which causes said processors to process a substantially equal number of packets.

3. The method of claim 1, wherein said information includes a predetermined number of bits in at least one header field of said packet.

4. The method of claim 3, wherein said header field contains at least one of source identification information and exchange originator identification information for said packet.

5. The method of claim 1, wherein said mapping function assigns packets from a same sequence to a same one of said plurality of processors.

6. The method of claim 1, wherein said mapping function is a hash function.

7. The method of claim 6, further comprising:

storing said packet in the memory unit,

wherein said hash function transforms a key that specifies a set of items into a table address, said key corresponding to at least one header field of said packet, said set of items including a plurality of received packets, and said table address corresponding to a selection of said one of said plurality of processors.

8. The method of claim 7, further comprising:

sending pointer information to said one of said plurality of processors, said pointer information indicating a location of said packet stored in said memory unit.

9. The method of claim 6, wherein said hash function is implemented by one of logical and arithmetic instructions, a hardwired circuit, and a table lookup.

10. The method of claim 6, wherein said packet is transmitted using a fibre channel protocol, and wherein said header information includes source identification information and exchange originator identification data.

11. A device for routing packets in a network, comprising:

an input port for receiving a packet that includes header information;

a plurality of processors;

a memory unit; and

a direct memory access (DMA) device which performs a mapping function that includes assigning said packet based on said header information, and which routes said packet to one of said plurality of processors based on the assignment performed by said mapping function.

12. The device of claim 11, wherein said mapping function assigns a plurality of packets in a manner which causes said processors to process a substantially equal number of packets.

13. The device of claim 11, wherein said direct memory access device stores said packet in the memory unit.

14. The device of claim 11, wherein said direct memory access device sends pointer information to said one of said plurality of processors, said pointer information indicating a location of said packet stored in said memory unit.

15. The device of claim 11, further comprising:

at least one queue,

wherein said direct memory access device stores pointer information in said queue, said pointer information indicating a location where said packet is stored in the memory unit, and

wherein said one of said plurality of processors reads said pointer information from said queue to access the packet stored in the memory unit.

16. The device of claim 15, wherein said queue is a FIFO buffer.

17. The device of claim 15, wherein said queue is a ring buffer.