Mechanism for the dynamic detection of graph based connectivity among PCI devices

• US 20030069961A1
• Filed: 10/04/2001
• Published: 04/10/2003
• Est. Priority Date: 10/04/2001
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kumar, Mohan J., Kaushik, Shivnandan D., Rankin, Linda J., Crossland, James B., OʼShea, David J.
• Application Number:
  US09/972,108
• Publication Number:
  US 20030069961A1
• Time in Patent Office: Days
• US Class Current: 709/224
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A method and apparatus for the dynamic detection of graph-based connectivity among PCI (Peripheral Component Interconnect) devices are disclosed. A connectivity capability structure of a device and a list of connection records for the device are used to determine connectivity information for the device.

Claims

1. A method comprising:

receiving a connectivity capability structure of a device;

receiving a list of connection records for the device; and

determining connectivity information for the device.

2. The method according to claim 1, wherein the device is a Peripheral Component Interconnect (PCI) device.

3. The method according to claim 2, wherein the connectivity capability structure is an indicator of a type of connection from a current PCI device.

4. The method according to claim 3, wherein the connectivity capability structure further comprises an indicator for a number of connectivity ports on the PCI device.

5. The method according to claim 1, wherein the connectivity capability structure comprises:

a capability identifier;

a pointer to a next capability structure;

an indicator of a type of connection from a current device;

an indicator of a number of connectivity ports on a device; and

an indicator of a location of a number of connection records on a device.

6. An apparatus comprising:

a device; and

a processor coupled to the device for retrieving information on a connectivity capability structure of the device, and retrieving information on a list of connection records of the device.

7. The apparatus of claim 6, further comprising an operating system executing on the processor.

8. The apparatus of claim 6, wherein the device is a PCI device.

9. A machine-readable medium having stored thereon instructions, which when executed by a processor, causes said processor to perform the following:

receive a connectivity capability structure of a device;

receive a list of connection records for the device; and

determine connectivity information for the device.

10. The machine-readable medium according to claim 9, wherein receiving the connectivity capability structure of the device is receiving the connectivity capability structure of a PCI device.

11. The machine-readable medium according to claim 10, wherein receiving the connectivity capability structure of the PCI device comprises receiving an indicator of a type of connection from a current PCI device.

12. A system comprising:

a plurality of processors;

a plurality of devices coupled to the plurality of processors;

a first memory coupled to the processor and containing a connectivity capability structure for the plurality of devices coupled to the plurality of processors; and

a second memory coupled to the processor and containing a list of connection records for the plurality of devices coupled to the plurality of processors.

13. The system of claim 12, wherein the plurality of devices is a plurality of PCI devices.

14. The system of claim 12, wherein the first memory and the second memory are a single memory storage device.

15. An apparatus comprising:

a processor; and

a memory coupled to the processor, the memory comprising;

data on a capability identification of a first device coupled to the processor;

data on a pointer to a next capability structure of a second device coupled to the processor;

data on a connectivity type for the first device;

data on a number of connectivity ports for the first device; and

data on the location of a number of connection records for the first device.

16. The apparatus of claim 15, wherein the first device and the second device are PCI devices.

17. The apparatus of claim 15, wherein the apparatus further comprises a plurality of devices coupled to the processor.

18. An apparatus comprising:

means for receiving a connectivity capability structure of a device;

means for receiving a list of connection records for the device; and

means for determining connectivity information for the device.

19. The apparatus of claim 18, wherein means for receiving is a means for receiving from a memory device.

20. The apparatus of claim 18, wherein means for determining connectivity information for the device further comprises means for extracting information from the connectivity capability structure and the list of connection records to determine the connectivity information for the device.

21. A method comprising:

(a) inputting connectivity capability structure data of a device;

(b) inputting list of connection records data of the device; and

(c) determining a connectivity of the device. repeating the sequence (a)-(c) for a plurality of devices.

22. The method of claim 21 wherein the devices are PCI devices.

23. The method of claim 21 wherein the method is performed dynamically.