Bus control system
First Claim
1. A bus control method for use in a data processing system having a plurality of modules connected to at least one bus and adopting a split transfer protocol in which a start cycle and a response cycle of a read access operation of each of the modules is separated from each other with respect to time, comprising the steps of:
- assigning identifiers to said plurality of modules, respectively;
outputting, when a split read operation is initiated from a source module to an access destination module, an address specifying the destination module and identifier information representing an identifier of the source module from the source module; and
outputting, when a response is achieved from the destination module to the source module, response data of the split read operation and said identifier information from the destination module.
0 Assignments
0 Petitions
Accused Products
Abstract
In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.
69 Citations
11 Claims
-
1. A bus control method for use in a data processing system having a plurality of modules connected to at least one bus and adopting a split transfer protocol in which a start cycle and a response cycle of a read access operation of each of the modules is separated from each other with respect to time, comprising the steps of:
-
assigning identifiers to said plurality of modules, respectively;
outputting, when a split read operation is initiated from a source module to an access destination module, an address specifying the destination module and identifier information representing an identifier of the source module from the source module; and
outputting, when a response is achieved from the destination module to the source module, response data of the split read operation and said identifier information from the destination module. - View Dependent Claims (2, 3, 4, 5, 6, 7)
-
-
8. A data processing system adopting a split transfer protocol in which a start cycle and a response cycle of a read access operation is separated from each other with respect to time, comprising:
-
a system bus;
a plurality of bus adapters connected to the system bus, the adapters being assigned with identifiers, respectively; and
an identifier transfer line for transferring identifier information representing an identifier, wherein;
when a source bus adapter initiates a split read operation to an access destination bus adapter, the source adapter outputs an address specifying the destination adapter onto the system bus and identifier information representing an identifier of the source adapter onto the identifier transfer line; and
when the destination adapter achieves a response to the source adapter, the destination adapter outputs response data of the split read operation onto the system bus and said identifier information representing the identifier of the source adapter onto the identifier transfer line. - View Dependent Claims (9)
-
-
10. A data processing system adopting a split transfer protocol in which a start cycle and a response cycle of a read access operation is separated from each other with respect to time, comprising:
-
a system bus and a processor bus which are arranged in a hierarchic structure;
a plurality of processors connected to the processor bus, the processors being assigned with identifiers, respectively;
a plurality of bus adapters connected to the system bus, the adapters being assigned with identifiers, respectively; and
an identifier transfer line for transferring identifier information representing an identifier, wherein;
when a processor as a source unit initiates a split read operation to an access destination bus adapter, the source processor outputs an address specifying the destination adapter onto the system bus via at least one bus adapter and identifier information representing an identifier of the source processor onto the identifier transfer line; and
when the destination adapter achieves a response to the source processor, the destination adapter outputs response data of the split read operation onto the system bus via at least one bus adapter and said identifier information representing the identifier of the source processor onto the identifier transfer line.
-
-
11. A data processing system adopting a split transfer protocol in which a start cycle and a response cycle of a read access operation is separated from each other with respect to time, comprising:
-
a system bus and a processor bus which are arranged in a hierarchic structure;
a plurality of processors connected to the processor bus, the processors being assigned with identifiers, respectively;
a plurality of bus adapters connected to the system bus, the adapters being assigned with identifiers, respectively;
a plurality of I/O devices connected to the I/O bus, the I/O devices being assigned with identifiers, respectively; and
an identifier transfer line for transferring identifier information representing an identifier, wherein;
when a processor as a source unit initiates a split read operation to an access destination I/O device, the source processor outputs an address specifying the destination I/O bus onto the system bus via at least one bus adapter and identifier information representing an identifier of the source processor onto the identifier transfer line; and
when the destination I/O device achieves a response to the source processor, the destination I/O device outputs response data of the split read operation onto the system bus via at least one bus adapter and and said identifier information representing the identifier of the source processor onto the identifier transfer line.
-
Specification