Processor provided with a slow-down facility through programmed stall cycles

• US 20030070107A1
• Filed: 07/29/2002
• Published: 04/10/2003
• Est. Priority Date: 08/01/2001
• Status: Active Grant

• Current Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Reimens, Abraham Karel, Woods, Nathan
• Granted Patent: US 6,917,365 B2
• Time in Patent Office: Days
• US Class Current: 713/600
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A processor executes image processing under control of a clock facility, such that a sequence of C effective clock cycles will effect a processing operation of a predetermined amount of image information. In particular, the processor has programming means for implementing programmable stall clock cycles interspersed between the effective clock cycles for implementing a programmable slowdown factor S, such that a modified number of C*S overall clock cycles will effect processing of the predetermined amount of digital signal information.

Claims

1. A processor for executing digital signal processing under control of a clock facility, such that a sequence of C effective clock cycles will effect a processing operation of a predetermined amount of digital signal information,

said processor being characterized in having programming means for implementing programmable stall clock cycles interspersed between said effective clock cycles for implementing a programmable slowdown factor S, such that a modified number of C*S overall clock cycles will effect processing of said predetermined amount of digital signal information.

2. A processor as claimed in claim 1, and having said programming means controlling the interspersing in an at least substantially periodical manner.

3. A processor as claimed in claim 1, effectively representing a coprocessor and having a control processor as said programming means.

4. A processor as claimed in claim 3, wherein said coprocessor and said control processor are interconnected by a bus to a shared memory facility.

5. A processor as claimed in claim 4, wherein said coprocessor, said control processor and said bus are disposed on a single semiconductor chip, whereas said shared memory facility is at least substantially off-chip.

6. A processor as claimed in claim 1, and being arranged to execute at least two different modes, the modes being characterized by requiring respective different amounts of data to be processed under respective different percentages of stall clock cycles.

7. A processor as claimed in claim 1, said stall cycles being generated by a floating point to integer conversion.

8. A processor as claimed in claim 1, wherein said programming means drive an incrementable storage facility through a periodical increment by a number N that is a function of said factor S according to N=round (R*x), wherein x=(S−

1/S) and R is the range of the storage facility, and wherein a carry output signal of the storage facility will generate a stall cycle.

9. A processor as claimed in claim 1, wherein said programming means drive an arithmetic element that is arranged for executing an addition or subtraction operation with regard to a programmed value, and said addition or subtraction will in a first case produce a carry or borrow signal, respectively, and in a second case not produce such carry signal or borrow signal, respectively, and wherein a transition from a stall cycle to an effective processing cycle will be controlled by a transition between said first and second states.

10. A processor as claimed in claim 5, wherein at least one other bus station than the coprocessor is allowed to grab the bus in a time interval during a said stall cycle.

11. A processor as claimed in claim 1, furthermore having an origin for controlling second stall cycles, and comprising a detection facility for detecting an excessive number of said programmable stall cycles and said second stall cycles combined, and said processor having a control facility fed by said detection facility for then amending a recurrency of said programmable stall cycles.

12. A processor as claimed in claim 11, wherein said detection facility is arranged for generating an interrupt signal.

13. A processor as claimed in claim 11, wherein said detection facility is arranged for letting a bus arbiter allocate more bandwidth to the coprocessor in question.

14. A processor as claimed in claim 1, furthermore having an origin for controlling second stall cycles, and comprising a detection facility for detecting an excessive number of said programmable stall cycles and said second stall cycles combined, and said processor having a control facility fed by said detection facility for then amending one or more control parameters of the coprocessor through exploiting its scalability.