Built-in self-testing of multilevel signal interfaces

• US 20030070126A1
• Filed: 09/14/2001
• Published: 04/10/2003
• Est. Priority Date: 09/14/2001
• Status: Abandoned Application

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Zerbe, Jared L., Werner, Carl W., Stonecypher, William F.
• Application Number:
  US09/953,514
• Publication Number:
  US 20030070126A1
• Time in Patent Office: Days
• US Class Current: 714/715
• CPC Class Codes: G01R 31/31715 Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

Error detection mechanisms for signal interfaces are disclosed, including built-in self-test (BIST) mechanisms for testing multilevel signal interfaces. The error detection mechanisms may be provided in an integrated circuit (IC) chip that contains at least one of the signal interfaces or may be coupled to the interfaces on a printed circuit board (PCB). BIST mechanisms may include, for example, test signal generators and mechanisms for determining whether the test signals generated are accurately transmitted and received by the interface. The BIST mechanisms may check a single input/output interface, a group of interfaces or may operate with a master device that tests a plurality of interfaces. The error detection mechanisms may be particularly advantageous for testing memory circuits designed to communicate according to multi-PAM signals over printed circuit boards.

Claims

1. A device comprising:

a signal generator adapted to generate a test signals,

a transmit mechanism operably coupled to said signal generator and adapted to output a first multilevel signal based on said test signal,

a receive mechanism operably coupled to said transmit mechanism and adapted to detect a signal that crosses at least two reference levels over time, said receive mechanism outputting a detected signal based on said first multilevel signal, and

a comparison mechanism operably coupled to said receive mechanism and adapted to compare said detected signal with a reference signal, and to output an error signal if said detected signal does not match said reference signals.

2. The device of claim 1, wherein said transmit mechanism and said receive mechanism are part of a signal interface unit.

3. The device of claim 1, wherein said transmit mechanism is part of a first signal interface unit, said receive mechanism is part of a second signal interface unit, said first signal interface unit includes a second receive mechanism and said second signal interface unit includes a second transmit mechanism.

4. The device of claim 3, further comprising a third interface unit having a third transmit mechanism and a third receive mechanism, wherein said third transmit mechanism is operably coupled to said second receive mechanism.

5. The device of claim 1, wherein said transmit mechanism and said receive mechanism are connected by a bus that is affixed to a printed circuit board.

6. The device of claim 1, wherein said transmit mechanism and said receive mechanism are contained in an integrated circuit.

7. The device of claim 1, wherein said signal generator, said transmit mechanism, said receive mechanism and said comparison mechanism are contained in an integrated circuit.

8. The device of claim 1, wherein said transmit mechanism is a master and said receive mechanism is a slave.

9. The device of claim 1, wherein said receive mechanism is a master and said transmit mechanism is a slave.

10. The device of claim 1, wherein said transmit mechanism includes a plurality of transmitters and said receive mechanism includes a plurality of receivers, with each of said transmitters being operably coupled to a corresponding one of said receivers.

11. The device of claim 1, wherein said transmit mechanism and said receive mechanism are operably coupled to a memory.

12. A device comprising:

a master element including a controller and a master signal interface containing a transmit mechanism and a receive mechanism, said master being coupled to a signal pathway,

a plurality of slave elements each including a slave signal interface containing a transmit mechanism and a receive mechanism, and being coupled to said signal pathway,

an error detection mechanism coupled to at least one of said signal interfaces, and

a plurality of signals communicated between said master signal interface and at least one of said slave signal interfaces over said signal pathway and checked by said error detection mechanism for errors.

13. The device of claim 12, wherein said transmit mechanisms and said receive mechanisms each include multilevel signaling mechanisms.

14. The device of claim 12, wherein said error detection mechanism is coupled to said one slave signal interface and said signals are sent from said master transmit mechanism to said receive mechanism of said one slave signal interface.

15. The device of claim 12, wherein said error detection mechanism is coupled to said master signal interface and said signals are sent from said one slave transmit mechanism to said master receive mechanism.

16. The device of claim 12, wherein said error detection mechanism is coupled to said master signal interface, said signals are sent from said master transmit mechanism to said receive mechanism of said one slave signal interface, and said signals are sent from said transmit mechanism of said one slave signal interface to said master receive mechanism.

17. The device of claim 12, wherein said master element and said slave elements are respective integrated circuits affixed to a printed circuit board.

18. The device of claim 12, wherein said slave elements include memory cells.

19. A device comprising:

a base,

first, second and third conductive paths affixed to said base,

a sequence generator affixed to said base, connectable to said first conductive path and configured to generate a first sequence of signals,

a driver circuit affixed to said base and connectable to said first and second conductive paths, said driver circuit adapted to input said first sequence of signals and output onto said second conductive path a signal having a voltage level that varies in time between at least three distinct levels,

a receiver circuit affixed to said base and connectable to said second and third conductive paths, said receiver circuit adapted to receive said signal, determine which of said at least three distinct levels exists at a given time, and output onto said third conductive path a second sequence of signals, and

an error detection mechanism affixed to said base, connectable to said third conductive path and adapted to determine whether said second sequence of signals matches said first sequence of signals.

20. The device of claim 19, wherein said driver circuit and said receiver circuit are part of a signal interface unit including an input/output pin connected to said second conductive path.

21. The device of claim 19, wherein said driver circuit is part of a first signal interface unit, said receiver circuit is part of a second signal interface unit, said first signal interface unit includes a second receiver circuit and said second signal interface unit includes a second driver circuit.

22. The device of claim 19, further comprising a third interface unit having a third driver circuit and a third receiver circuit, said third driver circuit connectable to said second receiver circuit by a fourth conductive path.

23. The device of claim 19, wherein said driver circuit controls said receiver circuit.

24. The device of claim 19, wherein said receiver circuit controls said driver circuit.

25. A device comprising a number of signal interface units configured to communicate in parallel, said signal interface units each having a transmit mechanism and a receive mechanism, with each transmit mechanism of a first set of said signal interface units being connectable to a receive mechanism of a second set of said signal interface units.

26. The system of claim 25, wherein said signal interface units communicate according to signals that vary in time between at least three distinct levels.