High performance system-on-chip using post passivation process

• US 20030071326A1
• Filed: 11/25/2002
• Published: 04/17/2003
• Est. Priority Date: 12/21/1998
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Granted Patent: US 6,897,507 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/642 : Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/647 : Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01084 : Polonium [Po]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: Y10S 257/92 : Conductor layers on different levels connected in parallel, e.g. to reduce resistance

Abstract

The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

Claims

1. A method for forming an inductor for high performance integrated circuits overlaying the surface of a semiconductor substrate, comprising:

providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;

creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;

depositing a passivation layer over said overlaying interconnecting metalization structure;

depositing a polymer insulating, separating layer over said passivation layer that is substantially thicker than said passivation layer and that is also substantially thicker than an inter-layer dielectric used for creating said interconnecting metallization structure;

forming openings through said polymer insulating, separating layer and through said passivation layer to expose at least one pair of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure;

filling said openings with a conductive material, creating metal contacts through said openings; and

forming said inductor on the surface of said polymer insulating, separating layer, said inductor being connected to at least one pair of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure.

2. The method of claim 1 wherein the size of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure is within the range of approximately 0.3 μ

m to 50 μ

m.

3. The method of claim 1 wherein said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure comprise a material that is selected from a group comprising sputtered aluminum, CVD tungsten, CVD copper, electroplated gold;

electroplated silver, electroplated copper, electroless gold and electroless nickel.

4. The method of claim 1 whereby said inductor is embedded in a dielectric and furthermore covered by a layer of passivation.

5. The method of claim 4 wherein said dielectric is a low-K dielectric.

6. The method of claim 1 with the addition of one or more layers of ferromagnetic material overlying said passivation layer with a thickness of between about 1,000 and 50,000 Angstrom and over a surface area that is about the surface area over which said inductor overlays said polymer insulating, separating layer, interspersing said one or more layers of ferromagnetic material between the surface of said passivation layer and the thereover deposited polymer insulating, separating layer.

7. The method of claim 1 wherein said inductor is of a spiral design and is created on the surface of said polymer insulating, separating layer and in a plane that is parallel to the plane of the surface of said polymer insulating, separating layer.

8. The method of claim 1 wherein said inductor is created using damascene processing procedures.

9. The method of claim 1 wherein said inductor is created using methods of photolithographic exposure and etching.

66. The method of claim 1 wherein said inductor is created overlying the surface of a layer of passivation whereby no layer of polymer is applied.

67. The method of claim 1 wherein said inductor is a solenoid structure overlying a layer of polymer, said layer of polymer overlying a layer of passivation.

68. The method of claim 1 wherein said inductor is a solenoid structure overlying a layer of passivation whereby no layer of polymer is applied.

79. The method of claim 1 with the addition of one or more layers of conductive material overlying said passivation layer over a thickness of between about 1,000 and 50,000 Angstrom and over a surface area that is about the surface area over which said inductor overlays said polymer insulating, separating layer, interspersing said one or more layers of conductive material between the surface of said passivation layer and the thereover deposited polymer insulating, separating layer.

80. The method of claim 1 wherein said inductor is a toroidal design and is created on the surface of said polymer insulating, separating layer.

83. The method of claim 1 wherein said inductor is a toroidal coil structure overlying a layer of polymer, said layer of polymer overlying a layer of passivation.

84. The method of claim 1 wherein said inductor is a toroidal coil overlying a layer of passivation whereby no layer of polymer is applied.

10. A method for forming a capacitor for high performance integrated circuits on the surface of a semiconductor substrate, said capacitor comprising a top plate and a bottom plate and a layer of dielectric interspersed between said top and said bottom plate, comprising:

providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;

creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate, said points of electrical contact provided on the surface of said overlaying interconnecting metalization structure being divided into pairs of even and odd numbered adjacent contact points whereby one point of electrical contact can belong to only one pair;

depositing a passivation layer over said overlaying interconnecting metalization structure;

patterning and etching said layer of passivation, creating openings in said layer of passivation, at least one opening overlaying at least one even contact point of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure;

depositing a first layer of conductive material over the surface of said layer of passivation, including said openings created in said layer of passivation;

patterning and etching said first layer of conductive material creating an opening to at least one of said even numbered points of electrical contact provided in or on the surface of said overlaying interconnecting metalization structure, creating said bottom plate of said capacitor;

depositing a layer of dielectric over the surface of said first layer of conductive material, including said opening to at least one of said even numbered points of electrical contact;

patterning and etching said layer of dielectric, creating an opening in said layer of dielectric to at least one of said even numbered points of electrical contact, partially exposing at least one of said even numbered points of electrical contact, creating said layer of dielectric interspersed between said top plate and said bottom plate;

depositing a second layer of conductive material over the surface of said layer of dielectric, including at least one opening created in said layer of dielectric; and

patterning and etching said second layer of conductive material, creating said top plate of said capacitor.

11. The method of claim 10 with additional processing steps performed after said step of the patterning and etching said layer of passivation, comprising:

depositing a polymer insulating, separating layer over the surface of said patterned and etched layer of passivation, including said openings created in said layer of passivation; and

patterning and etching said polymer insulating, separating layer, creating at least one opening in said polymer insulating, separating layer that aligns with at least one of said even numbered points of electrical contact on the surface of said overlaying interconnecting metalization structure.

12. The method of claim 11 wherein said polymer insulating, separating layer is of a thickness after curing within the range of approximately 1.0 to 150 μ

m.

13. The method of claim 11 wherein said polymer insulating, separating layer is spin-on coated and cured.

69. The method of claim 11 wherein said polymer insulating, separating layer is laminated dry film.

14. A method for forming a resistor for high performance integrated circuits on the surface of a semiconductor substrate, comprising:

providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;

creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;

depositing a passivation layer over said overlaying interconnecting metalization structure;

patterning and etching said layer of passivation, creating openings in said layer of passivation, at least two of said openings overlaying at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization;

depositing a layer of conductive material over the surface of said layer of passivation, including said openings created in said layer of passivation;

patterning and etching said layer of resistive conducting material, creating a layer of conductive material that interconnects at least one pair of said openings created in said layer of passivation, creating said resistor.

15. A method for forming a resistor for high performance integrated circuits on the surface of a semiconductor substrate, comprising:

providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;

creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;

depositing a passivation layer over said overlaying interconnecting metalization structure;

patterning and etching said layer of passivation, creating openings in said layer of passivation, at least two of said openings overlaying and partially exposing at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure;

depositing an polymer insulating, separating layer over the surface of said patterned and etched layer of passivation, including said openings created in said layer of passivation;

patterning and etching said polymer insulating, separating layer, creating at least one pair of openings in said polymer insulating, separating layer that aligns with at least one pair of openings created in said layer of passivation, partially exposing at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure;

depositing a layer of conductive material over the surface of said polymer insulating, separating layer including said openings created in said polymer insulating, separating layer; and

patterning and etching said layer of resistive conducting material, creating a layer of conductive material that interconnects at least one pair of said openings created in said layer of passivation, creating said resistor.

16. The method of claim 15 wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 μ

m of Plasma Enhanced CVD (PECVD) oxide over which a layer within the range of approximately 0.5 to 2.0 μ

m PECVD nitride is deposited.

17. The method of claim 15 wherein said polymer insulating, separating layer comprises polyimide or the polymer benzocyclobutene (BCB).

18. The method of claim 15 wherein said polymer insulating, separating layer is of a thickness after curing within the range of approximately 1.0 to 150 μ

m.

19. The method of claim 15 wherein said polymer insulating, separating layer is spin-on coated and cured.

20. The method of claim 19 wherein said polymer insulating, separating layer is subjected to multiple processing steps of spin on coating and curing.

70. The method of claim 15 wherein said polymer insulating, separating layer is laminated dry film.

21. A method for mounting a discrete electrical component above the surface of a semiconductor substrate, comprising:

providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;

creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;

depositing a passivation layer over said overlaying interconnecting metalization structure;

patterning and etching said layer of passivation, creating openings in said layer of passivation, at least two of said openings overlaying at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure, providing at least one pair of points of electrical contact in said layer of passivation;

depositing an polymer insulating, separating layer over the surface of said patterned and etched layer of passivation, including said openings created in said layer of passivation;

patterning and etching said polymer insulating, separating layer, creating at least one pair of openings in said polymer insulating, separating layer that aligns with at least one pair of points of electrical contact provided in said layer of passivation;

selectively depositing a layer of conductive material over the surface of at least one pair of points of electrical contact provided in said layer of passivation, filling said openings created in said polymer insulating, separating layer, creating conductive plugs through said polymer insulating, separating layer, said conductive plugs overlaying at least one pair of points of electrical contact provided in said layer of passivation,

selectively creating a layer of solder over the surface of said conductive plugs;

positioning said discrete electrical component above and in alignment with said selectively created layer of solder such that electrical contact points of said discrete electrical component align with said selectively created layer of solder; and

flowing said selectively created layer of solder, creating solder balls connecting said discrete electrical component with said conductive plugs in said polymer insulating, separating layer, thereby connecting said discrete electrical component with a pair of points of electrical contact in said layer of passivation.

22. The method of claim 21 wherein said polymer insulating, separating layer comprises a polyimide or the polymer benzocyclobutene (BCB).

23. The method of claim 21 wherein said polymer insulating, separating layer is of a thickness after curing within the range of approximately 1.0 to 150 μ

m.

24. The method of claim 21 wherein said polymer insulating, separating layer is subjected to multiple processing steps of spin on coating and curing.

25. The method of claim 21 wherein said discrete electrical component is selected from a group comprising a resistor, a capacitor and an inductor.

71. The method of claim 21 wherein said solder ball is created by electroplating, electroless plating, screen printing, and ball mounting.

72. The method of claim 21 wherein said polymer insulating, separating layer is laminated dry film.

26. A method for mounting a discrete electrical component above the surface of a semiconductor substrate, comprising:

providing a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;

creating an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;

depositing a passivation layer over said overlaying interconnecting metalization structure;

patterning and etching said layer of passivation, creating openings in said layer of passivation, at least two of said openings overlaying at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure, providing at least one pair of points of electrical contact in said layer of passivation;

selectively creating a layer of solder over the surface of at least one pair of points of electrical contact in said layer of passivation;

positioning said discrete electrical component above and aligned with said selectively created layer of solder such that electrical contact points of said discrete electrical component align with said selectively created layer of solder; and

flowing said layer of selectively created solder, creating solder balls connecting said discrete electrical component with at least one pair of points of electrical contact in said layer of passivation.

27. The method of claim 26 wherein said discrete electrical component is selected from a group comprising a resistor, a capacitor and an inductor.

28. An inductor for high performance integrated circuits overlaying the surface of a semiconductor substrate, comprising:

a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;

an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;

a passivation layer deposited over said overlaying interconnecting metalization structure;

a polymer insulating, separating layer deposited over said passivation layer that is substantially thicker than said passivation layer and that is also substantially thicker than an inter-layer dielectric used for creating said interconnecting metallization structure;

openings formed through said polymer insulating, separating layer and through said passivation layer to expose at least one pair of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure;

said openings filled with a conductive material, creating metal contacts through said openings; and

said inductor formed on the surface of said polymer insulating, separating layer, said inductor being connected to at least one pair of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure.

29. The inductor of claim 28 wherein the size of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure is within the range of approximately 0.3 μ

m to 50 μ

m.

30. The inductor of claim 28 wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 μ

m of Plasma Enhanced CVD (PECVD) oxide over which a layer within the range of approximately 0.5 to 2.0 μ

m PECVD nitride is deposited.

31. The inductor of claim 28 wherein said polymer insulating, separating layer comprises polyimide or the polymer benzocyclobutene (BCB).

32. The inductor of claim 28 wherein said polymer insulating, separating layer is of a thickness after curing within the range of approximately 1.0 to 150 μ

m.

33. The inductor of claim 28 wherein said polymer insulating, separating layer is spin-on coated and cured.

34. The inductor of claim 28 wherein said polymer insulating, separating layer is subjected to multiple processing steps of spin on coating and curing.

35. The inductor of claim 28 wherein said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure comprise a material that is selected from a group comprising sputtered aluminum, CVD tungsten, CVD copper, electroplated gold, electroplated copper, electroplated silver, electroless gold and electroless nickel.

36. The inductor of claim 28 whereby said inductor is embedded in a dielectric and furthermore covered by a layer of passivation.

37. The inductor of claim 36 wherein said dielectric is a low-K dielectric.

38. The inductor of claim 28 with the addition of one or more layers of ferromagnetic material overlying said passivation layer over a thickness of between about 2,000 and 50,000 Angstrom and over a surface area that is about the surface area over which said inductor overlays said polymer insulating, separating layer, interspersing said one or more layers of ferromagnetic material between the surface of said passivation layer and the thereover deposited polymer insulating, separating layer.

39. The inductor of claim 28 wherein said inductor is of a spiral design and is created on the surface of said polymer insulating, separating layer and in a plane that is parallel to the plane of the surface of said polymer insulating, separating layer.

40. The inductor of claim 28 wherein said inductor is created using damascene processing procedures.

41. The inductor of claim 28 wherein said inductor is created using methods of photolithographic exposure and etching.

73. The inductor of claim 28 wherein said polymer insulating, separating layer is laminated dry film.

74. The inductor of claim 28 wherein said inductor is of a solenoid design and is created on the surface of said polymer insulating, separating layer, said solenoid comprising two patterned metal layers in overlying planes that are parallel to the plane of the surface of said polymer insulating, separating layer, said patterned metal layers being connected by vias, whereby said layer of polymer is deposited over the surface of a layer of passivation.

75. The inductor of claim 28 wherein said inductor is of a solenoid design and is created on the surface of said polymer insulating, separating layer, said solenoid comprising two patterned metal layers in overlying planes that are parallel to the plane of the surface of said polymer insulating, separating layer, said patterned metal layers being connected by vias, whereby said layer of polymer is deposited over the surface of a layer of polyimide, whereby said layer of polyimide is deposited over the surface of a layer of passivation.

81. The inductor of claim 28 with the addition of one or more layers of conductive material overlying said passivation layer over a thickness of between about 1,000 and 50,000 Angstrom and over a surface area that is about the surface area over which said inductor overlays said polymer insulating, separating layer, interspersing said one or more layers of conductive material between the surface of said passivation layer and the thereover deposited polymer insulating, separating layer.

82. The inductor of claim 28 wherein said inductor is a toroidal coil and is created on the surface of said polymer insulating, separating layer.

85. The inductor of claim 28 wherein said inductor is a toroidal coil and is created on the surface of said polymer insulating, separating layer, whereby said layer of polymer is deposited over the surface of a layer of passivation.

86. The inductor of claim 28 wherein said inductor is a toroidal coil and is created on the surface of said polymer insulating, separating layer, whereby said layer of polymer is deposited over the surface of a layer of polymer, whereby said layer of polymer is deposited over the surface of a layer of passivation.

42. A capacitor for high performance integrated circuits on the surface of a semiconductor substrate, said capacitor comprising a top plate and a bottom plate and a layer of dielectric interspersed between said top and said bottom plate, comprising:

a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;

an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate, said points of electrical contact provided on the surface of said overlaying interconnecting metalization structure being divided into pairs of even and odd numbered adjacent contact points whereby one point of electrical contact can belong to only one pair;

a passivation layer deposited over said overlaying interconnecting metalization structure;

openings created in said layer of passivation, at least one opening overlaying at least one even contact point of said points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure;

a first layer of conductive material deposited over the surface of said layer of passivation, including said openings created in said layer of passivation;

an opening created in said first layer of conductive material to at least one of said even numbered points of electrical contact provided in or on the surface of said overlaying interconnecting metalization structure, said first layer of conductive material forming said bottom plate of said capacitor;

a layer of dielectric deposited over the surface of said first layer of conductive material, including said opening to at least one of said even numbered points of electrical contact;

an opening in said layer of dielectric to at least one of said even numbered points of electrical contact, partially exposing at least one of said even numbered points of electrical contact, forming said layer of dielectric interspersed between said top plate and said bottom plate;

a second layer of conductive material deposited over the surface of said layer of dielectric, including at least one opening created in said layer of dielectric; and

said top plate of said capacitor created by patterning and etching said second layer of conductive material.

43. The capacitor of claim 42 with additionally comprising, over said patterned and etched said layer of passivation:

an polymer insulating, separating layer deposited over the surface of said patterned and etched layer of passivation, including said openings created in said layer of passivation; and

at least one opening created in said polymer insulating, separating layer that aligns with at least one of said even numbered points of electrical contact on the surface of said overlaying interconnecting metalization structure.

44. The capacitor of claim 42 wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 μ

m of Plasma Enhanced CVD (PECVD) oxide over which a layer within the range of approximately 0.5 to 2.0 μ

m PECVD nitride is deposited.

45. The capacitor of claim 43 wherein said polymer insulating, separating layer comprises polyimide or the polymer benzocyclobutene (BCB).

46. The capacitor of claim 43 wherein said polymer insulating, separating layer is of a thickness after curing within the range of approximately 1.0 to 150 μ

m.

47. The capacitor of claim 43 wherein said polymer insulating, separating layer is spin-on coated and cured.

76. The capacitor of claim 43 wherein said polymer insulating, separating layer is laminated dry film.

48. A resistor for high performance integrated circuits on the surface of a semiconductor substrate, comprising:

a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;

an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;

a passivation layer deposited over said overlaying interconnecting metalization structure;

openings created in said layer of passivation, at least two of said openings overlaying at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization;

a layer of resistive conducting material deposited over the surface of said layer of passivation, including said openings created in said layer of passivation; and

a layer of conductive material that interconnects at least one pair of said openings created in said layer of passivation, creating said resistor.

49. The resistor of claim 48 wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 μ

m of Plasma Enhanced CVD (PECVD) oxide over which a layer within the range of approximately 0.5 to 2.0 μ

m PECVD nitride is deposited.

50. A resistor for high performance integrated circuits on the surface of a semiconductor substrate, comprising:

a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;

an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided Lo said semiconductor devices in or on the surface of said substrate;

a passivation layer deposited over said overlaying interconnecting metalization structure;

openings created in said layer of passivation, at least two of said openings overlaying and partially exposing at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure;

a polymer insulating, separating layer deposited over the surface of said patterned and etched layer of passivation, including said openings created in said layer of passivation;

at least one pair of openings in said polymer insulating, separating layer that aligns with at least one pair of openings created in said layer of passivation, partially exposing at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure;

a layer of conductive material deposited over the surface of said polymer insulating, separating layer including said openings created in said polymer insulating, separating layer; and

a layer of resistive conducting material that interconnects at least one pair of said openings created in said layer of passivation, creating said resistor.

51. The resistor of claim 50 wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 μ

m of Plasma Enhanced CVD (PECVD) oxide over which a layer within the range of approximately 0.5 to 2.0 μ

m PECVD nitride is deposited.

52. The resistor of claim 50 wherein said polymer insulating, separating layer comprises a polymer dielectric comprises polyimide or the polymer benzocyclobutene (BCB).

53. The resistor of claim 50 wherein said polymer insulating, separating layer is of a thickness after curing within the range of approximately 1.0 to 150 μ

m.

54. The resistor of claim 50 wherein said polymer insulating, separating layer is spin-on coated and cured.

55. The resistor of claim 50 wherein said polymer insulating, separating layer is subjected to multiple processing steps of spin on coating and curing.

77. The resistor of claim 50 wherein said polymer insulating, separating layer is laminated dry film.

56. A discrete electrical component above the surface of a semiconductor substrate, comprising:

a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;

an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;

a passivation layer deposited over said overlaying interconnecting metalization structure;

openings created in said layer of passivation, at least two of said openings overlaying at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure, providing at least one pair of points of electrical contact in said layer of passivation;

an polymer insulating, separating layer deposited over the surface of said patterned and etched layer of passivation, including said openings created in said layer of passivation;

at least one pair of openings created in said polymer insulating, separating layer that aligns with at least one pair of points of electrical contact provided in said layer of passivation;

a layer of conductive material selectively deposited over the surface of at least one pair of points of electrical contact provided in said layer of passivation, filling said openings created in said polymer insulating, separating layer, creating conductive plugs through said polymer insulating, separating layer, said conductive plugs overlaying at least one pair of points of electrical contact provided in said layer of passivation;

a layer of solder selectively created over the surface of said conductive plugs;

said discrete electrical component positioned above and in alignment with said selectively created layer of solder such that electrical contact points of said discrete electrical component align with said selectively created layer of solder; and

said selectively created layer of solder flowed, creating solder balls connecting said discrete electrical component with said conductive plugs in said polymer insulating, separating layer, thereby connecting said discrete electrical component with a pair of points of electrical contact in said layer of passivation.

57. The discrete electrical component of claim 56 wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 μ

m of Plasma Enhanced CVD (PECVD) oxide over which a layer within the range of approximately 0.5 to 2.0 μ

m PECVD nitride is deposited.

58. The discrete electrical component of claim 56 wherein said polymer insulating, separating layer comprises polyimide or the polymer benzocyclobutene (BCB).

59. The discrete electrical component of claim 56 wherein said polymer insulating, separating layer is of a thickness after curing within the range of approximately 1.0 to 150 μ

m.

60. The discrete electrical component of claim 56 wherein said polymer insulating, separating layer is spin-on coated and cured.

61. The discrete electrical component of claim 56 wherein said polymer insulating, separating layer is subjected to multiple processing steps of spin on coating and curing.

62. The discrete electrical component of claim 56 wherein said discrete electrical component is selected from a group comprising a resistor, a capacitor and an inductor.

78. The discrete electrical component of claim 56 wherein said polymer insulating, separating layer is laminated dry film.

63. A discrete electrical component mounted above the surface of a semiconductor substrate, comprising:

a semiconductor substrate, in or on the surface of which semiconductor devices have been created, having points of electrical contact provided to said semiconductor devices in or on the active surface of said substrate;

an overlaying interconnecting metalization structure comprising one or more layers of interconnects over the active surface of said substrate, said layers of interconnects comprising conductive interconnect lines or conductive contact points or conductive vias in one or more layers, with points of electrical contact having been provided in or on the surface of said overlaying interconnecting metalization structure, at least one of said points of electrical contact making contact with at least one of said conductive interconnect lines or said conductive contact points or said conductive vias provided in said one or more layers of said overlaying interconnecting metalization structure, at least one of said metal lines or said contact points or said conductive vias making contact with at least one of said points of electrical contact provided to said semiconductor devices in or on the surface of said substrate;

a passivation layer deposited over said overlaying interconnecting metalization structure;

openings created in said layer of passivation, at least two of said openings overlaying at least one pair of points of electrical contact having been provided in the surface of said overlaying interconnecting metalization structure, providing at least one pair of points of electrical contact in said layer of passivation;

a layer of solder selectively deposited over the surface of at least one pair of points of electrical contact in said layer of passivation;

said discrete electrical component positioned above and aligned with said selectively deposited layer of solder such that electrical contact points of said discrete electrical component align with said selectively deposited layer of solder; and

said layer of selectively deposited solder flowed, creating solder balls connecting said discrete electrical component with at least one pair of points of electrical contact in said layer of passivation.

64. The discrete electrical component of claim 63 wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 μ

m of Plasma Enhanced CVD (PECVD) oxide over which a layer within the range of approximately 0.5 to 2.0 μ

m PECVD nitride is deposited.

65. The discrete electrical component of claim 63 wherein said discrete electrical component is selected from a group comprising a resistor, a capacitor and an inductor.