APPARATUS AND METHOD FOR LEADLESS PACKAGING OF SEMICONDUCTOR DEVICES

• US 20030071335A1
• Filed: 10/16/2001
• Published: 04/17/2003
• Est. Priority Date: 10/16/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeung, Boon Suan, Poo, Chia Yong, Waf, Low Siu
• Granted Patent: US 6,747,348 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24998 Reinforcing structures, e.g. ramp-like support
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48147 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48699 Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
• CPC Class Codes: H01L 2224/48744 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82007 : involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
• CPC Class Codes: H01L 2224/82951 : Forming additional members
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06551 : Conductive connections on the side of the device
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 : of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07025 : Polyimide
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

The present invention is directed to a leadless and interconnected semiconductor package. The package includes a first chip having bond pads with a second chip having bond pads positioned on the first chip to form a vertically stacked package. Interconnections between the bond pads are formed by metallized layers on the package that extend to an edge of the package to join castellations along sides of the package to form a plurality of leadless input/output locations for the package. In one embodiment, the castellations include planar metallized portions. In another embodiment, the castellations include semi-cylindrical metallized portions. In still another embodiment, insulators are positioned between the chips, and on the package base. In still another embodiment, a chip includes a photosensitive device having screening optical layers. Bond pads on the chip are electrically coupled to castellations extending from the bond pads to form leadless input/output locations for the package.

Claims

1. A semiconductor package, comprising:

a first semiconductor chip having an upper surface;

a second semiconductor chip having an upper surface and an opposing lower surface, the lower surface of the second chip being positioned on the upper surface of the first chip to define an exposed portion of the upper surface of the first chip, the first chip further including a first plurality of bond pads disposed on the exposed portion, and the second chip further including a second plurality of bond pads disposed on the upper surface of the second chip;

a plurality of interconnections that extend from the first plurality of bond pads to the second plurality of bond pads, the interconnections being disposed on selected portions of the first and second chips to electrically couple the first and second chips; and

a plurality of castellations disposed on selected portions of the first chip that extend outwardly from the first plurality of bond pads to form leadless input/output locations for the package.

2. The semiconductor package according to claim 1 wherein the second semiconductor chip is further comprised of a peripheral surface that extends between the upper and the lower surface, and further wherein the plurality of interconnections disposed on selected portions of the first and second chips extend inwardly along the upper surface of the first chip from the first plurality of bond pads and extend upwardly along the peripheral surface to the second plurality of bond pads.

3. The semiconductor package according to claim 1 wherein the first semiconductor chip is further comprised of a lower surface having a lower edge, the lower surface opposing the upper surface and having a peripheral surface that extends between the upper and the lower surfaces.

4. The semiconductor package according to claim 3 wherein the plurality of castellations is further comprised of a plurality of planar members that extend upwardly from the lower edge and along the peripheral surface to the first plurality of bond pads.

5. The semiconductor package according to claim 3 wherein the plurality of castellations is further comprised of a plurality of semi-circular members each having an axis that is approximately parallel to the peripheral surface that extend inwardly into the peripheral surface and upwardly from the lower edge to the first plurality of bond pads.

6. The semiconductor package of claim 1, further comprising a dielectric layer interposed between the plurality of interconnections and the first and second chips.

7. The semiconductor package of claim 1, further comprising a dielectric layer interposed between the plurality of castellations and the first chip.

8. The semiconductor package of claim 1, further comprising a dielectric layer disposed on the second chip that substantially encapsulates the second chip and extends onto at least a portion of the first chip.

9. The semiconductor package according to claim 3, further comprising a n insulating layer disposed on the lower surface of the first chip.

10. The semiconductor package according to claim 9, wherein the insulating layer is comprised of a dielectric polymer.

11. The semiconductor package according to claim 9, wherein the insulating layer is comprised of a glass substrate.

12. The semiconductor package of claim 1, further comprising an insulating layer interposed between the first and second chips.

13. The semiconductor package according to claim 12, wherein the insulating layer is further comprised of a dielectric adhesive.

14. The semiconductor package according to claim 12, wherein the insulating layer is further comprised of a dielectric polymer adhesively joined to the upper surface of the first chip and the lower surface of the second chip.

15. The semiconductor package according to claim 12, wherein the insulating layer is further comprised of a glass substrate adhesively joined to the upper surface of the first chip and the lower surface of the second chip.

16. The semiconductor package according to claim 12, wherein the insulating layer is further comprised of a self-adhering dielectric film.

17. The semiconductor package according to claim 1 wherein the plurality of interconnections are further comprised of a plurality of metallic films.

18. The semiconductor package according to claim 17 wherein the plurality of metallic films are comprised of aluminum.

19. The semiconductor package according to claim 17 wherein the plurality of metallic films are comprised of copper.

20. The semiconductor package according to claim 17 wherein the plurality of metallic films are comprised of a refractory metal.

22. The semiconductor package according to claim 1 wherein the plurality of castellations are further comprised of a plurality of metallized films.

23. The semiconductor package according to claim 22 wherein the plurality of metallic films are comprised of aluminum.

24. The semiconductor package according to claim 22 wherein the plurality of metallic films are comprised of copper.

25. The semiconductor package according to claim 22 wherein the plurality of metallic films are comprised of a refractory metal.

21. The semiconductor package according to claim I wherein the plurality of interconnections further comprises a plurality of bonding wires that extend from the first plurality of bond pads to the second plurality of bond pads.

26. A semiconductor package, comprising:

a first semiconductor chip having an upper surface;

a second semiconductor chip having an upper surface and an opposing lower surface, the lower surface of the second chip being positioned on the upper surface of the first chip to define an exposed portion of the upper surface of the first chip, the first chip further including a first plurality of bond pads disposed on the exposed portion, and the second chip further including a second plurality of bond pads disposed on the upper surface of the second chip;

a plurality of wire bond elements that extend from the first plurality of bond pads to the second plurality of bond pads to electrically couple the first and second chips; and

a plurality of castellations disposed on selected portions of the first chip that extend outwardly from the first plurality of bond pads to form leadless input/output locations for the package.

27. The semiconductor package according to claim 26 wherein the first semiconductor chip is further comprised of a lower surface having a lower edge, the lower surface opposing the upper surface and having a peripheral surface that extends between the upper and the lower surfaces.

28. The semiconductor package according to claim 27 wherein the plurality of castellations is further comprised of a plurality of planar members that extend upwardly from the lower edge and along the peripheral surface to the first plurality of bond pads.

29. The semiconductor package according to claim 27 wherein the plurality of castellations is further comprised of a plurality of semi-circular members each having an axis that is approximately parallel to the peripheral surface that extend inwardly into the peripheral surface and upwardly from the lower edge to the first plurality of bond pads.

30. The semiconductor package of claim 26, further comprising a dielectric layer interposed between the plurality of castellations and the first chip.

31. The semiconductor package of claim 26, further comprising a dielectric layer disposed on the second chip that substantially encapsulates the second chip and extends onto at least a portion of the first chip.

32. The semiconductor package according to claim 27, further comprising an insulating layer disposed on the lower surface of the first chip.

33. The semiconductor package according to claim 32, wherein the insulating layer is comprised of a dielectric polymer.

34. The semiconductor package according to claim 32, wherein the insulating layer is comprised of a glass substrate.

35. The semiconductor package of claim 26, further comprising an insulating layer interposed between the first and second chips.

36. The semiconductor package according to claim 35, wherein the insulating layer is further comprised of a dielectric adhesive.

37. The semiconductor package according to claim 35, wherein the insulating layer is further comprised of a dielectric polymer adhesively joined to the upper surface of the first chip and the lower surface of the second chip.

38. The semiconductor package according to claim 35, wherein the insulating layer is further comprised of a glass substrate adhesively joined to the upper surface of the first chip and the lower surface of the second chip.

39. The semiconductor package according to claim 35, wherein the insulating layer is further comprised of a self-adhering dielectric film.

40. The semiconductor package according to claim 26 wherein the plurality of castellations are further comprised of a plurality of metallized films.

41. The semiconductor package according to claim 40 wherein the plurality of metallic films are comprised of aluminum.

42. The semiconductor package according to claim 40 wherein the plurality of metallic films are comprised of copper.

43. The semiconductor package according to claim 40 wherein the plurality of metallic films are comprised of a refractory metal.

44. A package for a photosensitive device capable of sensing incident light, comprising:

a semiconductor chip having an upper surface that supports the photosensitive device, the chip having a plurality of bond pads exposed at the upper surface that are coupled to the device;

at least one optical layer disposed on the photosensitive device; and

a plurality of castellations disposed on selected portions of the chip that extend outwardly from the bond pads to form a plurality of leadless input/output locations for the package.

45. The package according to claim 44 wherein the semiconductor chip is further comprised of an opposing lower surface having a lower edge and a peripheral surface that extends between the upper surface and the lower surface.

46. The package according to claim 45 wherein the plurality of castellations is further comprised of a plurality of planar members extending upwardly from the lower edge and along the peripheral surface to the bond pads.

47. The package according to claim 45 wherein the plurality of castellations is further comprised of a plurality of semi-circular members each having an axis that is approximately parallel to the peripheral surface that extend inwardly into the peripheral surface and upwardly from the lower edge to the plurality of bond pads.

48. The package of claim 44, further comprising a dielectric layer interposed between the castellations and the chip.

49. The package according to claim 45, further comprising an insulating layer disposed on the lower surface of the chip.

50. The package according to claim 49, wherein the insulating layer is comprised of a dielectric polymer.

51. The package according to claim 49, wherein the insulating layer is comprised of a glass substrate.

52. The package according to claim 44 wherein the plurality of castellations are further comprised of a plurality of metallized films.

53. The package according to claim 52 wherein the plurality of metallic films are comprised of aluminum.

54. The package according to claim 52 wherein the plurality of metallic films are comprised of copper.

55. The package according to claim 52 wherein the plurality of metallic films are comprised of copper.

56. The package according to claim 52 wherein the plurality of metallic films are comprised of a refractory metal.

57. A method for forming a leadless, interconnected semiconductor package, comprising:

disposing a second semiconductor chip onto a first semiconductor chip, each chip having a plurality of exposed bond pads;

forming a plurality of interconnections that extend from bond pads on the first chip to corresponding bond pads on the second chip; and

forming a plurality of castellations that extend from the bond pads on the first chip.

58. The method according to claim 57 wherein the step of disposing is further comprised of bonding the second chip to the first chip with an adhesive.

59. The method according to claim 57 wherein the step of bonding is further comprised of bonding the second chip to the first chip using an double-backed adhesive tape.

60. The method according to claim 57 wherein the step of disposing is further comprised of interposing an insulating layer between the first and second semiconductor chips.

61. The method according to claim 57 wherein the step of forming a plurality of interconnections further comprises:

applying a dielectric layer to a surface portion of the first and the second semiconductor chips; and

depositing a metallic film on the dielectric layer.

62. The method according to claim 57 wherein the step of forming a plurality of castellations further comprises:

applying a dielectric layer to a surface portion of the first semiconductor chip; and

depositing a metallic film on the dielectric layer.

63. The method according to claim 57 further comprising:

applying a dielectric layer to the second semiconductor chip that extends at least partially onto a surface of the first semiconductor chip.

64. A method for fabricating a plurality of vertically stacked, interconnected and leadless semiconductor packages, comprising:

supporting a substrate having a plurality of first semiconductor chips formed therein, the first chips having a first plurality of bond pads exposed at an upper surface of the substrate;

positioning a plurality of second semiconductor chips onto the substrate, each second chip being positioned on a single first chip and having a second plurality of bond pads;

depositing a plurality of interconnections onto the first chips and the second chips that extend between corresponding bond pads on the first and second chips;

singulating the substrate to obtain a plurality of separated semiconductor packages; and

depositing a plurality of castellations to the first chips that extend outwardly from the first plurality of bond pads.

65. The method according to claim 64 wherein the step of positioning is further comprised of bonding the second chips to the substrate using an adhesive.

66. The method according to claim 64 wherein the step of bonding is further comprised of applying one side of a double-backed adhesive tape to the substrate;

and disposing the second chip onto an opposing side of the double-backed adhesive tape.

67. The method according to claim 64 wherein the step of depositing a plurality of interconnections further comprises:

depositing a dielectric layer onto selected surface portions of the first and second chips; and

forming a metallic film on the dielectric layer.

68. The method according to claim 64 wherein the step of depositing a plurality of castellations further comprises:

depositing a dielectric layer onto selected surface portions of the first chips; and

forming a metallic film on the dielectric layer.

69. The method according to claim 64 wherein the step of singulating the substrate further comprises:

thinning the substrate at a lower surface that opposes the upper surface to obtain a thinned substrate; and

dicing the thinned substrate to form a plurality of separated semiconductor packages.

70. The method according to claim 64 wherein the step of singulating the substrate further comprises:

forming a plurality of holes that project through the substrate that are positioned between adjacent first chips;

thinning the substrate at a lower surface that opposes the upper surface to obtain a thinned substrate; and

dicing the thinned substrate along a direction that substantially bisects the holes.

71. The method according to claim 70 wherein the step of thinning the substrate is further comprised of backgrinding the substrate.

72. The method according to claim 64, further comprising applying a dielectric layer to the second semiconductor chips that substantially encapsulates the second chips and at least partially extends onto the first chips.

73. A method for fabricating a plurality of photosensing packages, comprising:

supporting a substrate having a plurality of photosensitive devices formed on an upper surface of the substrate, each photosensitive device having a plurality of bond pads disposed on the upper surface;

disposing at least one optical layer onto the photosensitive device;

forming a plurality of drains in the upper surface of the substrate that are positioned between adjacent photosensitive devices and project at least partially into the substrate;

thinning the substrate at a lower surface that opposes the upper surface to expose the plurality of drains; and

depositing a plurality of castellations onto the packages that extend outwardly from the plurality of bond pads.

74. The method according to claim 73 wherein the step of depositing a plurality of castellations further comprises:

depositing a dielectric layer onto selected surface portions of the package; and

forming a metallic film on the dielectric layer.

75. The method according to claim 73 wherein the step of thinning the substrate further comprises:

forming a plurality of holes that project through the substrate that are positioned between adjacent photosensitive devices;

backgrinding the substrate at the lower surface to obtain a thinned substrate; and

dicing the thinned substrate along a direction that substantially bisects the holes.

76. The method according to claim 73 wherein the step of disposing at least one optical layer onto the photosensitive device further comprises positioning an optical layer onto the photosensitive device that substantially blocks infrared radiation.

77. The method according to claim 73 wherein the step of disposing at least one optical layer onto the photosensitive device further comprises applying an optical layer by spin coating an optically transparent material onto the photosensitive device.

78. The method according to claim 77 wherein the step of applying an optical layer by spin coating an optically transparent material onto the photosensitive device is further comprised of planarizing a surface of the optical layer.

79. The method according to claim 73 wherein the step of disposing at least one optical layer onto the photosensitive device further comprises:

sputtering a layer of an optically transparent material onto the photosensitive device; and

planarizing the sputtered layer to obtain an optically flat surface.

80. The method according to claim 73 wherein the step of disposing at least one optical layer onto the photosensitive device further comprises:

growing an epitaxial layer on the photosensitive device; and

planarizing the epitaxial layer to obtain an optically flat surface.